微米尺度覆晶銲點於高電流密度與溫度控制下之微結構發展

Abstract

電子產品隨著時代推演，朝向更多功能以及更容易攜帶等方向發展，因此其中的積體電路（Integrated Circuit, IC）亦隨著國際半導體技術藍圖（The International Technology Roadmap for Semiconductors, ITRS）的規劃、各大研究機構與法人不斷發展新的製造技術使單位面積上的電晶體增加。同時因為晶片功能性的增加，必須增加晶片的I/O（Input�Output）數，覆晶封裝(Flip-Chip Package)技術因此成為高階電子元件的封裝技術，特別是使用線寬為奈米尺度先進製程的中央處理單元（Central Process Unit, CPU）、繪圖處理單元（Graphic Process Unit, GPU）與動態隨機存取記憶體（Dynamic Random Access Memory, DRAM）等高階晶片都仰賴此一技術封裝。 根據2010年版本的ITRS，第一級封裝的凸塊間距（Bump Pitch）將由2010年的50微米縮小至2012年的40微米，於2016年時將進一步縮小至35微米。於如此小的間距下，而凸塊的直徑勢必比間距更小，伴隨而來的是極高電流密度下的電遷移效應（Electromigration）。 前人探討覆晶銲點電遷移時，多數是以電流密度輔以環境溫度的控制作為實驗條件，對於通電的晶片而言，焦耳熱效應會使得受測系統的溫度上升高於環境溫度，在高電流密度的電遷移實驗特別明顯。吾人知道於無鉛銲點系統中，以錫為主要成分的銲點會在攝氏兩百二十度左右熔融，而且不論是以銅或者鎳為Under Bump Metallurgy（UBM）的系統，都會在攝氏一百度的溫度下於合理的測試時間（兩千小時）內有顯著的固態化學反應，使得銲點中的銲料與UBM反應為介金屬化合物（Intermetallic Compounds, IMCs），改變銲點系統的微結構以及顯微組織。因此不僅電遷移效應本身會造成銲點系統的改變，高溫本身也會對吾人研究的系統造成影響。 為了將焦耳熱效應的影響降到最低，本實驗將輔以油浴冷卻系統將晶片本身的溫度降至50度，並以105安培每平方公分的高電流密度對凸塊間距20微米的微小凸塊作400、800、1200、1600及2000個小時的電遷移試驗，凸塊的直徑為12微米，而在凸塊對接前的微結構為Al(8kA)/Cu(5μm)/Ni(3μm)/Sn-2.5Ag(5μm)，並將通電試驗完畢的試片作冷鑲埋與研磨拋光，輔以掃描式電子顯微鏡（Scanning Electron Microscope, SEM）拍攝顯微組織並以能量分散式X光光譜儀（Energy-dispersive X-ray Spectroscopy, EDS）作顯微組織的分析以及成分組成鑑定，並對其微結構的變化作一探討與解釋。 由電阻量測的結果中顯示，即使於超高電流密度下，因為輔以冷卻裝置做散熱，在通電測試的2000個小時後此一晶片的鏈(daisy chain)結構仍能正常導通，電阻值的上升比率為44%。

Progression over time, electronic products developed to be multi-function and ultra-portable. Hence, the ICs’(Integrated Circuits) configuration also according to the roadmap of ITRS(The International Technology Roadmap for Semiconductors), researching institutes and companies are developing cutting-edge IC producing technologies, that makes number of transistor on each IC to steps up. Meanwhile, because of multi-function of the chips, that needs to raise the I/O counts, so flip-chip package technology becomes the candidate that packaging these advancing chips. Especially for high-I/O counts chips like CPUs(Central Process Unit), GPUs(Graphic Process Unit) and DRAMs(Dynamic Random Access Memory). According to the ITRS 2010 edition, bump pitch of first level package will shrink down from 50 micron to 40 micron in 2012 by 2 years, and 35 micron at 2016. Under such nearing bump pitch, bump diameter should be closer than bump pitch, accompanying electromigration effect under ultra-high current density. Formers discussed electromigration effect in solder joint, most of them used constant current density and constant environment temperature. But, for conducting chips, Joule heating effect will raise the temperature and higher than environment temperature, especially under ultra-high current density condition. We know in lead-free solder systems, the melting points are around 220 degree Celsius, and no matter with Cu or Ni UBM, solid state chemical reaction will occur to form IMCs(Intelmetallic Compounds) under 100 degree Celsius, this outcome altering the solder-bump microstructure and texture. Hence not only the conducting current varying solder-bump system, but also the temperature, too. In order to cancel out the influence of Joule heating effect, the experimental uses oil-cooling system as a heat sink, reducing the chip temperature to 50 degree Celsius and applied with ultra-high current density of 105 Ampere per square centimeter. Tests were conducted with 400, 800, 1200, 1600 and 2000 hour. The bump pitch is 20 micron and the bump diameter is 12 micron. The bump configuration before face-to-face bonding is Al(8kA)/Cu(5μm)/Ni(3μm)/Sn-2.5Ag(5μm). After the test, chips was cold-mounted, grinded and polished. Examined bump microstructure by SEM(Scanning Electron Microscope) and specified phase composition by EDS(Energy-dispersive X-Ray Spectroscopy). Even though the ultra-high current density was conducted, the daisy chain on chip can still carry current after 2000 hours test. This result confirmed by resistance measuring. The resistance increment ratio was 44%.