請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29636完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥(Sy-Yen Kuo) | |
| dc.contributor.author | Yen-Ting Liu | en |
| dc.contributor.author | 劉彥廷 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:13:01Z | - |
| dc.date.available | 2007-07-27 | |
| dc.date.copyright | 2007-07-27 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-20 | |
| dc.identifier.citation | [1] Chunjie Duan, Anup Tirumala and Sunil P. Khatri, “Analysis and Avoidance of Cross-talk in On-Chip Buses,” in Proceeding of Symposium on High Performance Interconnects Hot Interconnects, pp. 133-138, 2001.
[2] Andre K. Nieuwland, Atul Katoch, Daniele Rossi, and Cecilia. Metra, “Coding Techniques for Low Switching Noise in Fault Tolerant Busses,” in Proceeding of International On-Line Testing Symposium, pp. 183-189, 2005 [3] Bret Victor and Kurt Keutzer, “Bus Encoding to Prevent Crosstalk Delay,” in Proceeding of International Conference on Computer Aided Design, pp. 57–69, 2001. [4] Dennis Sylvester and Kurt Keutzer, “Getting to the Bottom of Deep Submicron” in Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, pp. 203-221 1998 [5] Kei Hurise and Hiroto Yasuura “A Bus Delay Reduction Technique Considering Crosstalk,” in Electronics and Communications in Japan, Part 3, Vol. 85, No. 1, pp. 441-445, 2002 [6] Iris Hui-Ru Jiang, Yao-Wen Chang, and Jing-Yang Jou, “Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 9, pp. 999–1010, Sep 2000 [7] Chapiro, D. M., “Globally-Asynchronous Locally-Synchronous systems”, PH.D. dissertation, Stanford University, Stanford, California, USA, Oct. 1984 [8] Jens Muttersbach, Thomas Villiger, and Wolfgang Fichtner, “Practical Design of Globally-Asynchronous Locally-Synchronous Systems,” in Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 52-59, 2000 [9] T. Sakurai and K. Tamaru, “Simple Formulas for Two and Three Dimensional Capacitance,” in IEEE Trans. Electron Devices, pp. 183–185, 1983. [10] D. Rossi, S. Cavallotti, C. Metra, “Error Correcting Codes for Crosstalk Effect Minimization,” in Proceeding of International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 257-264, 2003. [11] Lei He and Kevin M. Lepak, “Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization,” in Proceeding of International Symposium on Physical Design, pp. 56-61, 2000. [12] Junmou Zhang and Eby G. Friedman, “Effect of Shield Insertion on Reducing Crosstalk Noise between Coupled Interconnects,”in Proceeding of International Symposium on Circuits and Systems, pp. 529-532, 2004. [13] D. Rossi, S. Cavallotti, C. Metra, “Error Correcting Codes for Crosstalk Effect Minimization,” in Proceeding of International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 257-264, 2003. [14] M. Stan and W. Burlson. “Bus-Invert Coding for Low Power I/O”. In Transaction on VLSI Systems, volume 3, pp. 49-58, March 1995 [15] D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland, and C. Metra, “Coding Scheme for Low Energy Consumption Fault-Tolerant Bus,” in Proceeding of On-line Testing Workshop, pp. 8–12, 2002. [16] Tiehan Lv, Jorg Henkel, Haris Lekatsas, and Wayne Wolf, “Enhancing Signal Integrity through a Low-overhead Encoding Scheme on Address Buses,” in Proceeding of Design Automation and Test in Europe, pp. 542-547, 2003. [17] Matheos Lampropoulos, Bashir M Al-Hashimi, and Paul Rosinger, “Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique,” in Proceeding of Design Automation and Test in Europe, pp. 1372-1373, 2004. [18] Sunil P. Khatri, Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics. PhD thesis, UC Berkeley, Dec 1999. [19] T. Sakurai and K. Tamaru, “Simple Formulas for Two and Three Dimensional Capacitance,” in IEEE Trans. Electron Devices, pp. 183–185, 1983. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29636 | - |
| dc.description.abstract | 隨著製程縮減至奈米規模以及系統晶片大行其道下，雜訊干擾的問題已經是一個不容忽視的問題。特別是在GALS(Globally Asynchronous Locally Synchronous)系統下，晶片設計師採用了大量的非同步匯流排作為溝通之用。可以預見的是，未來雜訊干擾的問題在非同步匯流排下必定會更為嚴重。因此我們提出了一個再非同步匯流排下減少傳送資料時所產生的耦合電容的方法。實驗結果顯示出我們的方法可以得到多達20% 的改進，再平均情況下也可以減少18% 的雜訊干擾。即使加上了面積的考量，我們的演算法也可以增加多達10個百分點的效能。 | zh_TW |
| dc.description.abstract | With the process shrinking to nanometer scale and the popularity of SoC, the crosstalk issue becomes un-ignorable. Especially in the GALS systems, designers adopt asynchronous buses for communication purpose. The crosstalk effect will be a critical issue on the asynchronous bus in the future. Thus, we propose a method under an asynchronous bus to reduce the coupling capacitance induced while transmitting. Experimental results show that our method will gain up to 20% improvement and 18% on average. Even if we take the area overhead into consideration, we could still have up to 10% improvement. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:13:01Z (GMT). No. of bitstreams: 1 ntu-96-R94943149-1.pdf: 281217 bytes, checksum: 563dc33aab856de63aa8a2bd0d31e5e1 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Content
Acknowledgements iii 摘要 v Abstract vii Content ix List of Tables xi List of Figures xiii Chapter 1. Introduction 1 1.1. Motivation 1 1.2. Introduction to Crosstalk 3 1.3. Introduction to Bus 6 1.4. Organization of the Thesis 7 Chapter 2. Preliminary 8 2.1. Pervious Work 8 2.2. Assumptions 11 2.3. Crosstalk Modeling 13 2.4. Problem Formulation 15 Chapter 3. Our Algorithm 19 3.1. Our method 19 3.1.1. The Detecting Component 19 3.1.2. The Inverse Component 21 3.1.3. The Recovery Component 22 3.2. Circuit Realization and Discussion 23 3.2.1. The Detecting Component 23 3.2.2. The Inverse Component 24 3.2.3. The Recovery Component 26 3.3. Proof for Correctness 27 Chapter 4. Experimental Results 31 Chapter 5. Conclusions and Future Work 35 | |
| dc.language.iso | en | |
| dc.subject | 非同步 | zh_TW |
| dc.subject | 串訊 | zh_TW |
| dc.subject | 編碼 | zh_TW |
| dc.subject | 匯流排 | zh_TW |
| dc.subject | Minimization | en |
| dc.subject | Encoding | en |
| dc.subject | Bus | en |
| dc.subject | Asynchronous | en |
| dc.subject | Crosstalk | en |
| dc.title | 基於匯流排編碼之串訊干擾最小化 | zh_TW |
| dc.title | Bus Encoding for Crosstalk Minimization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆(Chin-Laung Lei),袁世一(Shih-Yi Yuan),呂學坤(Shyue-Kung Lu) | |
| dc.subject.keyword | 串訊,編碼,匯流排,非同步, | zh_TW |
| dc.subject.keyword | Asynchronous,Bus,Encoding,Crosstalk,Minimization, | en |
| dc.relation.page | 38 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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