使用電容量測曲線的低散逸因子區域來決定超薄閘極氧化層的厚度

Abstract

隨著深次微米 (Deep Submicron) 製程時代的來臨，電子元件的規格朝向輕薄簡便、卻又不失性能效率的趨勢邁進。以常用的MOS電晶體為例，閘極介電層的等效厚度 (EOT) 必須降至2.0 nm以下、甚至接近1.0 nm左右，才能因應閘極長度縮短與偏壓降低所帶來的挑戰，並且維持MOS電晶體中閘極對於通道調控的特性。 傳統上閘極介電層普遍是以二氧化矽 (SiO2) 作為絕緣材料，然而其厚度一旦縮減至2.0 nm以下，進入超薄氧化層範圍 (Ultrathin Range) 之後，由於漏電流的急遽增加，使得原先的C－V曲線在累積區 (Accumulation Region) 出現失真變形的現象，造成無法精準地量測出MOS元件的氧化層厚度。 在本篇論文的研究中，我們率先提出一個全新的氧化層厚度測定方法，透過選取C－V曲線上散逸因子 (Dissipation Factor) 數值足夠低的區域，再進行線性迴歸 (Linear Regression) 的分析，經由與已知厚度的理論C－V曲線對照，可以決定出正確的閘極氧化層厚度。在MOS元件尺寸日益縮減、閘極介電層邁向超薄範圍的同時，研發出一個更簡易且更準確的方法來決定超薄氧化層的厚度，此項方法也已經由實驗證明對於閘極絕緣層厚度為1.6 nm的MOS元件能夠計算出相當正確的結果。

With the expeditious development of modern CMOS technology, the equivalent oxide thickness (EOT) of gate dielectric is systematically downscaled into the ultrathin range (＜2.0 nm) and becomes a key factor in the precise determination of many device parameters, such as electron/hole mobility, oxide charge density, interface trap density, breakdown field strength, etc. However, C－V curves of ultrathin oxides near the accumulation region show a disposition to roll off abruptly due to exponentially-increasing leakage current and series resistance; hence the two-frequency correction method was proposed to work out an empirical solution based on three-element circuit model. Once the oxide thickness shrank down below 2.0 nm, the error of measured capacitance could be dreadfully large, unless the two frequencies were chosen with caution. In this work, a new approach to the estimation of ultrathin oxide thickness from C－V measurement has been demonstrated. By choosing an adequate interval on the C－V curve where the dissipation factor is low enough, we can perform a simple linear regression, then comparing the experimental slope with theoretical values to find out the actual oxide thickness. This technique is valid for a 1.6 nm SiO2 capacitor, while the two-frequency correction method can hardly determine the correct value.