快速高斯雜訊產生器之設計與實作

Abstract

In modern communication systems, powerful error control codes such as Turbo code and Low-Density Parity Check (LDPC) codes are employed to provide capacity approaching coding gains. Both of these codes have very low bit error rate. In order to properly verify these powerful error control codes, very long simulations in the order of billion samples are often necessary. Software-based simulation using Additive White Gaussian Noise (AWGN) is time consuming, and FPGA based simulations using hardware Gaussian noise generator reduce simulation time significantly. The throughput-area ratio is crucial to an AWGN generator because we can easily increase throughput by running multiple instances in parallel, and hence the chip size is the key point. Our design goal is to reduce chip size, increase throughput, and maintain noise quality at the same level of software programs. This thesis proposed architecture of a fast Gaussian noise generator base on Wallace method and this architecture has high throughput-area ratio. The noise quality of our design is very close to software programs. Implementation result of this design is at clock rate 183MHz and output two noise samples each clock ticks. And the throughput exceeds 18 billion by duplicating 100 instances. This high throughput would be capable of a verification part of next generation communication circuits.