請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28330完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Fei-Pei Lai) | |
| dc.contributor.author | Sheng-Hsin Fan | en |
| dc.contributor.author | 范聖欣 | zh_TW |
| dc.date.accessioned | 2021-06-13T00:05:20Z | - |
| dc.date.available | 2016-08-11 | |
| dc.date.copyright | 2011-08-11 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-07 | |
| dc.identifier.citation | [1] K. Pagiamtzis and A. Sheikholeslami, 'Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,' Solid-State Circuits, IEEE Journal of , vol.41, no.3, pp. 712- 727, March 2006.
[2] L.T. Clark, Byungwoo Choi, and M. Wilkerson, 'Reducing translation lookaside buffer active power,' Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on , vol., no., pp. 10- 13, 25-27 Aug. 2003. [3] V. Chaudhary, T.-H. Chen, F. Sheerin, and L.T. Clark, 'Critical race-free low-power nand match line content addressable memory tagged cache memory,' Computers & Digital Techniques, IET , vol.2, no.1, pp.40-44, January 2008. [4] C. Graff, M. Bereschinsky, M. Patel, and Li Fung Chang, 'Application of mobile IP to tactical mobile internetworking,' Military Communications Conference, 1998. MILCOM 98. Proceedings., IEEE , vol.2, no., pp.409-414 vol.2, 18-21 Oct 1998. [5] M. Kobayashi, T. Murase, and A. Kuriyama, 'A longest prefix match search engine for multi-gigabit IP processing,' Communications, 2000. ICC 2000. 2000 IEEE International Conference on , vol.3, no., pp.1360-1364 vol.3, 2000. [6] M. Nourani, D.S. Vijayasarathi, and P.T. Balsara, 'A Reconfigurable CAM Architecture for Network Search Engines,' Computer Design, 2006. ICCD 2006. International Conference on , vol., no., pp.82-87, 1-4 Oct. 2007. [7] D.S. Vijayasarathi, M. Nourani, M.J. Akhbarizadeh, and P.T. Balsara, 'Ripple-precharge TCAM: a low-power solution for network search engines,' Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on , vol., no., pp. 243- 248, 2-5 Oct. 2005. [8] M.J. Akhbarizadeh, M. Nourani, and C.D. Cantrell, 'Prefix segregation scheme for a TCAM-based IP forwarding engine,' Micro, IEEE , vol.25, no.4, pp. 48- 63, July-Aug. 2005. [9] M.J. Akhbarizadeh, M. Nourani, D.S. Vijayasarathi, and P.T. Balsara, 'PCAM: a ternary CAM optimized for longest prefix matching tasks,' Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on , vol., no., pp. 6- 11, 11-13 Oct. 2004. [10] Sungdae Choi, K. Sohn, and Hoi-Jun Yoo, 'A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture,' Solid-State Circuits, IEEE Journal of , vol.40, no.1, pp. 254- 260, Jan. 2005. [11] S.P.A. Kumar, 'High-performance Longest Prefix Match Logic Supporting Fast Updates for IP Forwarding Devices,' Advance Computing Conference, 2009. IACC 2009. IEEE International , vol., no., pp.794-799, 6-7 March 2009. [12] C.A. Zukowski and Shao-Yi Wang, 'Use of selective precharge for low-power on the match lines of content-addressable memories,' Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on , vol., no., pp.64-68, 11-12 Aug 1997. [13] A. Roth, D. Foss, R. McKenzie, and D. Perry, 'Advanced ternary CAM circuits on 0.13 μm logic process technology,' Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004 , vol., no., pp. 465- 468, 3-6 Oct. 2004. [14] Ilion Yi-Liang Hsiao, Ding-Hao Wang, and Chein-Wei Jen, 'Power modeling and low-power design of content addressable memories ,' Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol.4, no., pp.926-929 vol. 4, 6-9 May 2001. [15] A. Efthymiou and J.D. Garside, 'An adaptive serial-parallel CAM architecture for low-power cache blocks,' Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on , vol., no., pp. 136- 141, 2002. [16] A. Efthymiou and J.D. Garside, 'A CAM with mixed serial-parallel comparison for use in low energy caches,' Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.12, no.3, pp.325-329, March 2004. [17] Kuo-Hsing Cheng, Chia-Hung Wei, and Shu-Yu Jiang, 'Static divided word matching line for low-power Content Addressable Memory design,' Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , vol.2, no., pp. II- 629-32 Vol.2, 23-26 May 2004. [18] K. Pagiamtzis and A. Sheikholeslami, 'Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,' Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003 , vol., no., pp. 383- 386, 21-24 Sept. 2003. [19] I.M. Hyjazie and Chunyan Wang, 'An approach for improving the speed of content addressable memories,' Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on , vol.5, no., pp. V-177- V-180 vol.5, 25-28 May 2003. [20] M. Motomura, J. Toyoura, K. Hirata, H. Ooka, H. Yamada, and T. Enomoto, 'A 1.2-million transistor, 33 MHz, 20-bit dictionary search processor with a 160 kb CAM,' Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International , vol., no., pp.90-91, 14-16 Feb. 1990. [21] M. Motomura, J. Toyoura, K. Hirata, H. Ooka, H. Yamada, and T. Enomoto, 'A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM,' Solid-State Circuits, IEEE Journal of , vol.25, no.5, pp.1158-1165, Oct 1990. [22] K.J. Schultz and P.G. Gulak, 'Fully-parallel multi-megabit integrated CAM/RAM design,' Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on , vol., no., pp.46-51, 8-9 Aug 1994. [23] K.J. Schultz and P.G. Gulak, 'Fully parallel integrated CAM/RAM using preclassification to enable large capacities,' Solid-State Circuits, IEEE Journal of , vol.31, no.5, pp.689-699, May 1996. [24] R. Panigrahy and S. Sharma, 'Reducing TCAM power consumption and increasing throughput,' High Performance Interconnects, 2002. Proceedings. 10th Symposium on , vol., no., pp. 107- 112, 2002. [25] F. Zane, Girija Narlikar, and A. Basu, 'Coolcams: power-efficient TCAMs for forwarding engines,' INFOCOM 2003. Twenty-Second Annual Joint Conference of the IEEE Computer and Communications. IEEE Societies , vol.1, no., pp. 42- 52 vol.1, 30 March-3 April 2003. [26] C.S. Lin, J.C. Chang, and B.D. Liu, 'Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory,' Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on , vol.2, no., pp. 319- 324 vol.2, 2002. [27] Perng-Fei Lin and J.B. Kuo, 'A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme,' Solid-State Circuits, IEEE Journal of , vol.37, no.10, pp. 1307- 1317, Oct 2002. [28] H. Kadota, J. Miyake, Y. Nishimichi, H. Kudoh, and K. Kagawa, 'An 8-kbit content-addressable and reentrant memory,' Solid-State Circuits, IEEE Journal of , vol.20, no.5, pp. 951- 957, Oct 1985. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28330 | - |
| dc.description.abstract | 因為三位元內容可定址記憶體的快速搜尋特性，使得它在許多需要高速的設備中扮演著重要的特色，但是它的耗電量也非常的高。而在傳統的NOR-type三位元內容可定址記憶體的功率消耗主要是來自於動態功率消耗，在一次的搜尋當中，對每一條相符線都先做預先充電，之後再把比對錯誤的相符線做放電，由於比對錯誤的相符線遠比正確的占的多，因此大多數的相符線都被放電了，這造成了很大的功率消耗。在這篇論文中，我們根據IP字首存在三位元內容可定址記憶體裡的遮罩位元，當遮罩位元出現0時，有著連續性的特性，提出了一個分段式預充電技術應用在三位元內容可定址記憶體來減少動態功率的消耗。實驗結果顯示，在一般的情況下考慮功率和延遲，將相符線分成四段是最佳的分段，並且可以減少23.68%的功率消耗和額外的0.74ns延遲。 | zh_TW |
| dc.description.abstract | Due to the characteristic of high-speed search in Ternary Content Addressable Memory (TCAM), it plays an important role in many high-speed devices, however it consumes too much power. The power consumption in conventional NOR-type TCAM is mainly from the dynamic power consumption, in which precharging all the match lines and discharging mismatched match lines during a search operation. Since the number of mismatched match lines is much more than the matched ones, most of the match lines are discharged leading to high power consumption. In this thesis, based on the characteristic of IP prefix stored in TCAM, the mask bit “0” has a continuity property when “0” appears. Therefore, we proposed a method called segmented-precharge technique in TCAM to reduce dynamic power consumption. The experimental results show that the proposed TCAM design with 4 segments is the most appropriate considering power and delay, which has 23.68% power saving and 0.74ns delay in average-case compared to the conventional TCAM. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T00:05:20Z (GMT). No. of bitstreams: 1 ntu-100-R97922092-1.pdf: 2239094 bytes, checksum: 1d0ea7cb7de6e3419f2460b0400e7ff9 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 口試委員會審定書...........................................i
誌謝......................................................ii 中文摘要.................................................iii Abstract..................................................iv Contents...................................................v List of Figures..........................................vii List of Tables..........................................viii Chapter 1 Introduction....................................1 1.1 Concept of CAM and TCAM..............................1 1.2 Thesis Organization..................................2 Chapter 2 Background and Related Work.....................3 2.1 CAM Architecture.....................................3 2.2 CAM Cell Structure...................................5 2.3 TCAM Cell Structure..................................6 2.4 Match Line Structures................................8 2.4.1 NOR-type.........................................8 2.4.2 NAND-type........................................9 2.4.3 Comparison Between NOR-type and NAND-type.......10 2.5 Related Work in Reducing Power Consumption..........11 2.5.1 Circuit Level: Selective-Precharge Scheme.......12 2.5.2 Circuit Level: Pipelining Scheme................13 2.5.3 Architectural Level: Bank-Selection Scheme......14 2.5.4 Architectural Level: Pre-computation Scheme.....15 Chapter 3 Proposed Method................................17 3.1 Motivation..........................................17 3.2 Concept of Segmented-Precharge......................18 3.3 Circuit Behavior....................................20 Chapter 4 Experimental Results...........................21 Chapter 5 Conclusions and Future Work....................27 Reference ................................................28 | |
| dc.language.iso | en | |
| dc.subject | 延遲 | zh_TW |
| dc.subject | 三位元內容可定址記憶體 | zh_TW |
| dc.subject | 功率消耗 | zh_TW |
| dc.subject | 相符線 | zh_TW |
| dc.subject | 遮罩位元 | zh_TW |
| dc.subject | 連續性 | zh_TW |
| dc.subject | 分段式預充電 | zh_TW |
| dc.subject | Match line | en |
| dc.subject | Delay | en |
| dc.subject | Segmented-precharge | en |
| dc.subject | Continuity | en |
| dc.subject | Mask bit | en |
| dc.subject | Ternary Content Addressable Memory (TCAM) | en |
| dc.subject | Power consumption | en |
| dc.title | 低功率使用分段預充電技術的三位元內容可定址記憶體設計 | zh_TW |
| dc.title | Low Power TCAM Design using Segmented-Precharge Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張延任(Yen-Jen Chang),蔡坤霖,李鴻璋,薛智文 | |
| dc.subject.keyword | 三位元內容可定址記憶體,功率消耗,相符線,遮罩位元,連續性,分段式預充電,延遲, | zh_TW |
| dc.subject.keyword | Ternary Content Addressable Memory (TCAM),Power consumption,Match line,Mask bit,Continuity,Segmented-precharge,Delay, | en |
| dc.relation.page | 32 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-100-1.pdf 未授權公開取用 | 2.19 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。