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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊佳玲(Chia-Lin Yang) | |
dc.contributor.author | Chi-Feng Li | en |
dc.contributor.author | 李奇峰 | zh_TW |
dc.date.accessioned | 2021-06-12T18:22:33Z | - |
dc.date.available | 2008-08-28 | |
dc.date.copyright | 2007-08-28 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-08-20 | |
dc.identifier.citation | [1] J. Anderson and F. Najm. Active Leakage Power Optimization for FPGAs.
IEEE Transactions on Computer-Aided Design (TCAD), 25(3):423–437, 2006. [2] S. Banerjee, E. Bozorgzadeh, and N. Dutt. HW-SW Partitioning for Architectures with Partial Dynamic Reconfiguration. In Technical Report CECS-TR-05-02, UC Irvine, 2005. [3] S. Banerjee, E. Bozorgzadeh, and N. Dutt. Physically-Aware HW-SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration. In Proceedings of the 42th Conference on Design Automation (DAC), pages 335–340, Jun. 2005. [4] R. P. Bharadwaj, R. Konar, P. T. Balsara, and D. Bhatia. Exploiting Temporal Idleness to Reduce Leakage Power in Programmable Architectures. In Proceedings of the 10th Asia and South Pacific Design Automation Conference (ASPDAC), pages 651–656, Jan. 2005. [5] J. M. Cooly and J. W. Tukey. An Algorithm for the Machine Calculation of Complex Fourier Series. Mathmatics of Computation, 19:297–301, 1965. [6] R. P. Dick, D. L. Rhodes, and W. Wolf. TGFF: Task Graph For Free. In Proceedings of the 6th International Workshop on Hardware/Software Codesign (CODES), pages 597–101, 1998. [7] F. Engel, G. Heiser, P. Mumford, and K. P. nand C. Rizos. An Open GNSS Receiver Platform Architecture. In Proceedings of the International Symposium on GPS/Global Navigation Satellite System (GNSS), Dec. 2004. [8] S. P. Fekete, E. K´ohler, and J. Teich. Optimal FPGA Module Placement with Temporal Precedence Constraints. In Proceedings of the 4th Design, Automation and Test in Europe Conference and Exhibition, pages 658–665, Mar. 2001. [9] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan. Reducing Leakage Energy in FPGAs Using Region-Constrained Placement. In Proceedings of the 12th International Symposium on Field Programmable Gate Arrays (FPGA), pages 51–58, 2004. [10] S. Hauck. Configuration Pre-Fetch for Single Sontext Reconfigurable Processors. In Proceedings of the 6th International Symposium on Field Programmable Gate Arrays (FPGA), pages 65–74, Feb. 1998. [11] D. Lee, D. Blaauw, and D. Sylvester. Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits. Transactions on Very Large Scale Integration Systems (TVLSI), 12(2), Feb. 2004. [12] F. Li, D. Chen, L. He, and J. Cong. Architecture Evaluation for Power-Efficient FPGAs. In Proceedings of the 11th International Symposium on Field Programmable Gate Arrays (FPGA), pages 175–184, Feb. 2003. [13] F. Li, Y. Lin, and L. He. FPGA Power Reduction Using Configurable Dual-Vdd. In Proceedings of the 41th Conference on Design Automation (DAC), pages 735–740, Jun. 2004. [14] A. Lodi, L. Ciccarelli, and R. Giansante. Combining LowLeakage Techniques for FPGA Routing Design. In Asia and South Pacific Design Automation Conference, 2005. [15] N. Lopez-Benitez and J.-Y. Hyon. Simulation of Task Graph Systems in Heterogeneous Computing Environments. In Proceedings of the 8th Heterogeneous Computing Workshop (HCW), pages 112–124, 1999. [16] A. Makhorin. GLPK (GNU Linear Programming Kit). http://www.gnu.org/software/glpk/, 2006. [17] Y. Meng, Y. Sherwood, and R. Kastner. Leakage Power Reduction of Embedded Memories on FPGAs Through Location Assignment. In Proceedings of the 43th Conference on Design Automation (DAC), pages 612–617, 2006. [18] A. Rahman and V. Polavarapuv. Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays. In Proceedings of the 12th International Symposium on Field Programmable Gate Arrays (FPGA), pages 23–30, Feb. 2004. [19] TORSCHE. TORSCHE Scheduling Toolbox for Matlab User’s Guide v0.2.0b2. In Matlab User’s Guide, page 61, 1999. [20] T. Tuan and B. Lai. Leakage Power Analysis of a 90nm FPGA. In Proceedings of the 22th IEEE Custom Integrated Circuits Conference, pages 57–60, Sept. 2003. [21] Xilinx. Virtex-II Pro and Virtex II Pro X FPGA User Guide. In Xilinx Inc., 2005. [22] P.-H. Yuh, C.-L. Yang, and Y.-W. Chang. Temporal Floorplanning Using the T-tree Formulation. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 300–305, 2004. [23] P.-H. Yuh, C.-L. Yang, Y.-W. Chang, and H.-L. Chang. Temporal Floorplanning using 3D-subTCG. In Proceedings of the 9th Asia and South Pacific Design Automation Conference (ASPDAC), pages 725–730, 2004. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27823 | - |
dc.description.abstract | 隨著製程技術進步到90奈米以下,在追求高效能和低功耗的嵌入式系統上使用可程式化邏輯閘陣列(Field-Programmable Gate Array, FPGA)時,降低漏電功耗(Leakage power)已經變成一項重要的議題。本篇論文著重於有睡眠電晶體(Sleep transistor)及預先載入機制(Prefetch technique)的可動態局部重組態可程式化邏輯閘陣列(Partially Dynamically Reconfigurable FPGAs)上,漏電功耗的問題。有可預先載入的機制下,一件工作可被切分為兩部分,一是用於重組局部FPGA的重組部分,另一個是執行工作功能的執行部分。我們專注於消除因重組(Reconfiguration)及任務執行(Task execution)之間的閒置延遲,而造成的虛耗漏電功耗(Leakage waste)。
我們提出依據整數線性規劃的方式求出最佳解以及一個不降低效能且減少虛耗漏電功耗的兩階段(Two-stage)排程/擺置法。第一階段,我們使用能有效縮短總執行時間的效能導向(Performance-driven)排程,產生符合單重組單元(Single Reconfiguration)和其他資源限制的正確擺置。第二個階段,我們使用擺置後(Post-placement)考量虛耗漏電功耗的排程演算法,用於改善前一個效能導向排程所產生的擺置,進而得到不犧牲效能且具有虛耗漏電功耗最小化的擺置。 在作用於真實與合成設計上所得的結果中,我們的兩階段演算法可以在較少的電腦計算時間下,得到接近由整數線性規劃表述所得出的最佳化虛耗漏電功耗。 | zh_TW |
dc.description.abstract | As technology advances to 90nm and below, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes imperative for adopting FPGAs in both high performance and low power embedded computing devices. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabric and the prefetch technique. Under the prefetch technique, a task is divided into the reconfiguration component that reconfigures a portion of FPGA for execution and execution component that
performs its functionality. We focus on eliminating leakage waste due to the delay between reconfiguration and execution points. We propose an optimal algorithm based on integer linear programming (ILP) and a two-stage task scheduling algorithm to reduce leakage power without sacrificing performance. In the first stage, we use a performance-driven task scheduler that minimizes the schedule length of an application to generate a feasible placement considering the single reconfiguration and resource constraints imposed by the target system. In the second stage, we perform post-placement leakage-aware task scheduling to minimize the leakage waste provided that the schedule length obtained by the performance-driven task scheduler is not increased. Experimental results on real and synthetic designs show that our two-stage algorithm can obtain near-optimal solution with less CPU time compared with the ILP formulation. | en |
dc.description.provenance | Made available in DSpace on 2021-06-12T18:22:33Z (GMT). No. of bitstreams: 1 ntu-96-R94922058-1.pdf: 1513911 bytes, checksum: 398cb5d935982e9fe27f40ef5527b139 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | Acknowledgements i
Chinese Abstract ii Abstract iii List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1 Overview of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Organization of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chapter 2. Related Work 5 Chapter 3. Preliminaries 7 3.1 Target FPGA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Performance-Driven Task Scheduling . . . . . . . . . . . . . . . . . . . . 8 Chapter 4. Scheduling Algorithm and Problem Formulation 10 4.1 ProblemFormulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.1 ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Post-Placement Leakage-Aware Task Scheduling Algorithm . . . . . . . . 14 4.2.1 ALAP Scheduling for Execution Components . . . . . . . . . . . . 17 4.2.2 Reconfiguration Component Clustering . . . . . . . . . . . . . . . 18 4.2.3 Reconfiguration Component Scheduling . . . . . . . . . . . . . . . 19 4.2.4 Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.5 Feasible Solution Guarantee . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 5. Experimental Results 25 5.1 Results on Real Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Results on Synthetic Designs . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 Effect of Task Parallelism. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Chapter 6. Conclusion 33 Bibliography 34 | |
dc.language.iso | en | |
dc.title | 於可動態局部重組邏輯閘陣列上考量漏電功耗之工作排程 | zh_TW |
dc.title | Leakage-Aware Task Scheduling
for Partially Dynamic Reconfigurable FPGAs | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張耀文(Yao-Wen Chang),顧孟愷(Mong-kai Ku),麥偉基(Wai-Kei Mak),阮聖彰(Shanq-Jang Ruan) | |
dc.subject.keyword | 可程式化邏輯閘陣列,擺置,漏電功耗,排程,效能, | zh_TW |
dc.subject.keyword | FPGA, Placement, Leakage, Scheduling, Performance, | en |
dc.relation.page | 36 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2007-08-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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