互補式金氧半延遲鎖定迴路在延遲產生與脈波寬度控制之設計與應用

Abstract

隨著積體電路系統的發展，對高頻率應用的需求也急速地增加。如此一來，精準的延遲產生器、同步問題和可變的工作週期也變得重要，但也變成高效能系統中亟需克服的瓶頸。 本研究分為兩個部份，第一個部份是針對延遲產生器，為了產生精準的相位，延遲產生器解析度的提升是必要的。在本研究中，我們提出一個利用平均時間延遲技巧的精準延遲產生器，藉由這個所提出的技巧，我們不但可以使用較小的晶片面積去達到低功率和高解析度的延遲產生器，而且可利用平均延遲技巧去獲得一個可變的延遲時間，而不是一個固定的延遲時間。本晶片使用0.18-μm CMOS 1P6M製程，在輸入操作頻率為400MHz下，解析度為25ps，在輸入1.8伏特的電壓下，總消耗功率為17毫瓦，全部的晶片面積佔了0.747×0.785mm2。 第二部份是針對脈波寬度控制迴路，一個系統在高速的操作下相位和工作週期是重要的資訊。在本研究中，我們使用0.18-μm CMOS 1P6M製程，提出一個具有可變的工作週期的脈波寬度控制迴路，並利用寬頻操作的延遲鎖定迴路。藉由這個所提出的技巧不但可以產生可變的工作週期信號，而且輸入和輸出信號的同步也可達到，輸出信號的工作週期可從30%到70%，每5%為一等級。而為了操作在輸入信號頻率介於400MHz到1.6GHz的寬頻範圍下，提出一個快速鎖定的起始電路去解決延遲鎖定迴路的鎖定錯誤問題。

As the development in VLSI systems, the demands of high frequency applications increase dramatically. Therefore, the precise delay generator, the synchronization problem, and programmable duty cycles are becoming important but choke points for high performance systems. This thesis is divided into two parts. The first part of the research is on delay generators. In order to generate precise phases, the resolution of delay generator enhancement is essential. In this work, we propose a precise delay generator circuit using an average delay technique. With the proposed technique, we can use not only smaller chip areas to achieve low power and a high resolution delay generator, but also the average delay technique to get a variable delay time, not a fixed one. The delay generator is realized in 0.18-μm CMOS 1P6M technology. The input frequency is 400MHz and the resolution is 25ps. Under a supply voltage of 1.8V, the whole chip ,which occupies the area of 0.747×0.785mm2 ,dissipates a power of 17mW. The second part of the research is on pulsewidth control loops (PWCL). In a high speed operation, the phase and the duty cycle are important information in a system. In this work, a pulsewidth control loop with a programmable duty cycle using a wide range DLL is realized in 0.18-μm CMOS 1P6M technology. Based on the proposed circuit, not only the programmable duty cycle of the clock can be generated but also the phase alignment between the input and output clocks can be achieved. The duty cycle of the output clock can be adjusted from 30% to 70% in steps of 5%. The input frequency is from 400MHz to 1.6GHz. In order to work in a wide range of operations, a fast locking started-controlled circuit (FLSC) is proposed to solve the harmonic problem in a DLL.