請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27459
標題: | 近橫向電磁合成傳輸線於互補金氧半導體製程上
的設計與應用 Design and Application of CMOS Synthetic Quasi-TEM Transmission Lines |
作者: | Meng-Ju Chiang 蔣孟儒 |
指導教授: | 莊晴光(Ching-Kuang C. Tzuang) |
關鍵字: | 傳輸線,合成波導,微波單晶積體電路, transmission line,0ynthetic guidied-wave,Monolithic Microwave Integrated Circuit, |
出版年 : | 2008 |
學位: | 博士 |
摘要: | 本篇論文係探討近橫向電磁合成傳輸線於互補金氧半導體製程 (CMOS) 上的理論、實驗及設計實例,並將此設計應用於射頻前端電路之縮小化設計以達成射頻系統單晶化。一旦近橫向電磁合成傳輸線(也稱做互補式金屬傳輸線 (CCS TL))之理論被建立後,此近橫向電磁合成傳輸線於標準0.18微米1P6M互補金氧半導體製程上的設計準則也就被確定。而近橫向電磁合成傳輸線是由五種結構參數來合成其波導特性以滿足設計的需求,其傳輸線特色包含有:一、設計出的合成傳輸線之特徵阻抗範圍為8.62歐姆至104.0歐姆;二、合成傳輸線最高的慢波係數可達4.79;三、經由理論與實驗證實此合成傳輸線面積與品質係數 (Q-factor) 成一比例關係,此比例可以幫助設計者評估在複雜的單晶化電路設計時會造成損耗值。此外,本篇論文首次提出將互補金氧半導體製程上重要的金屬密度規範引入傳輸線的設計考量。依據本論文所提出的設計法則所設計出的Ka-band 互補金氧半導體製程功率分配器 (Power Divider)、 180度耦合器 (Rat-Race Coupler) 及 90度耦合器 (Branch-Line Coupler) 等設計實例,經由量測證明互補式金屬傳輸線是一廣泛且有用的合成波導結構。
本論文的第二部份是提出利用互補式金屬傳輸線 (CCS TL)所設計之互補金氧半導體製程 (CMOS) 螺旋型電感,此電感即使在兩個電感非常靠近的情況下也能提供非常有效且寬頻的遮蔽效應,藉此隔離透過互補金氧半導體製程基板傳遞的耦合能量,與傳統未使用遮蔽設計的電感相比,隔離度有40 dB的改善。此外,一設計實例來論證互補式金屬傳輸線 (CCS TL)提供一完整金屬面來隔絕不同層的電磁耦合。基於此概念,本論文提出利用多層互補式金屬傳輸線,設計極小面積的Ka-band 功率分配器 (Power Divider)、 180度耦合器 (Rat-Race Coupler),其中功率分配器與180度耦合器面積分別為180.0 um × 180.0 um與210.0 um × 480.0 um。這些電路元件非常適合應用於單晶微波積體電路之系統整合。 本論文的第三部份是提出一互補金氧半導體製程 (CMOS) 邊緣耦合之互補式金屬耦合線 (CCS CL) 的結構,並利用此結構來設計 3-dB方向耦合器 (Directional Coupler)與平衡不平衡轉換器 (Marchand Balun)。3-dB方向耦合器的面積為120.0 um × 240.0 um,電路的頻率使用範圍為 14.2 GHz至36.9 GHz展現出其頻寬為 22.7 GHz。平衡不平衡轉換器 (Marchand Balun) 的頻率使用範圍為15.5 GHz至40.0 GHz。這兩種經由耦合線結構所設計出電路在寬頻及縮小化的方面具有極大的優勢。 最後,本論文提出設計於互補金氧半導體製程 (CMOS) 之Ka-band低功率零損耗全積體化主動帶通濾波器。主動濾波器中品質係數提升的共振器是由互補式金屬傳輸線 (CCS TL) 與負阻抗產生器 (Cross-Coupled Pair) 所組成。主動帶通濾波器的面積為275.0 um × 420.0 um,且電路允許 DC 電壓控制品質係數的提升。而在消耗3.7 mW 功率的情況下,此濾波器的特性為頻寬18.8 % 、1-dB 壓縮點(1-dB compression point (P1dB))為 -4.6 dBm、雜訊指數(noise figure (NF))為 7.0 dB。 此外,在窄頻的主動帶通濾波器設計方面,頻寬為8.2 %,其他特性皆與寬頻設計者相似。此設計展現了極佳的濾波器特性得以實際應用在射頻系統晶片上(RF SOC (system on chip))。 This dissertation presents theories, experiments and design examples necessary for carrying out synthesized quasi-TEM transmission lines (TLs) that lead to miniaturization of RF CMOS front-ends, making possible for achieving RF SOC (system on chip). Once the theoretical means for accurate assessment of the CMOS synthetic quasi-TEM lines, also known as complementary-conducting-strip transmission line (CCS TL), is established, the design guidelines of the synthetic quasi-TEM TL based on the standard 0.18-um one-poly six-metal (1P6M) CMOS technology is established. The synthetic CMOS CCS TL consists of five structural parameters such as the periodicity of the unit cell (P), the area of the mesh ground plane (Wh), central patch (W), the width of the connecting arms (S) and the number of metal layer to synthesize its guiding characteristics meeting various design requirements. The CMOS CCS TL shows the following unique properties: First, the characteristic impedance as low as 8.62 Ω and as high as 104.0 Ω has been practically demonstrated. Second, high slow-wave factor (SWF) of 4.79 has been shown. Third, constant ratio of the area occupied by the CCS TL to the corresponding quality factor (Q-factor) has been theoretically and experimentally confirmed, rendering accurate assessment of chip size and Q-factor of CCS TL before commencing the complex by SOC design. The new finding enables the RF SOC design methodology to trade off chip size and performance in the process of circuit miniaturization. CMOS CCS TL meets the metal density requirement, which has never been discussed before in our extensive literature search. By following the proposed design methodology of the CCS TL, several practical RF building blocks at Ka-band such as CMOS power divider, rat-race coupler and branch-line coupler had been designed and measured to the greatest accuracy possible to reveal the powerfulness of the synthetic CMOS CCS TL. Second, the complementary-conducting-strip transmission line (CCS TL) shows excellent shielding capability of 40.0 dB improvement over ordinary coupled inductors made on CMOS substrate. New CMOS spiral inductor made of CCS TL demands far less spacing between two CCS TL-based inductors from edge to edge when compared with the conventional spiral design. A design example is given to demonstrate excellent broadband shielding characteristic, taking advantage of the CCS TL ground plane which provides a complete conducting surface to isolate electromagnetic coupling between different layers. Based on such scheme, a multilayer CMOS CCS TL technology for the extremely compact RF hybrid designs has been developed. High-performance Ka-band power divider and rat-race coupler had been developed based on the stacked CMOS CCS TL scheme with effective area of 180.0 um × 180.0 um (4.21 × 10-4) and 210.0 um × 480.0 um (1.32 × 10-3), respectively. These miniaturized CCS-TL-based hybrids are ready for RF system integration in RF CMOS SOC. Third, the concept of CCS TL is extended the analysis and design of the edge-coupled complementary-conducting-strip coupled line (CCS CL) structure and applied for designing the coupled-line-based 3-dB directional coupler and Marchand balun. The 3-dB directional coupler shows the bandwidth of 22.7 GHz from 14.2 GHz to 36.9 GHz with an area of 120.0 um × 240.0 um and Marchand balun covers the frequency range from 15.5 GHz to 40.0 GHz, demonstrating the advantages of broader bandwidth and miniaturization in CMOS RF application. Finally, the low-power loss-free fully integrated active bandpass filters at Ka-band using a standard 0.18-um 1P6M CMOS technology are designed based on the CMOS CCS TL. A Q-enhanced resonator made of the complementary-conducting-strip transmission line (CCS TL), and an nMOS cross-coupled pair. The active size of bandpass filter measures 275.0 um × 420.0 um in size and the circuits allow DC voltage control for Q-enhancement. The bandpass filter has a 18.8 % bandwidth, exhibits a -4.6 dBm 1-dB compression point (P1dB) and noise figure (NF) of 7.0 dB while consuming 3.7 mW of DC power. The narrow-band bandpass filter with the bandwidth of 8.2 % exhibits similar performances with that of wide-band design. Such designs reveal excellent filter characteristics for practical application of RF SOC (system on chip). |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27459 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-97-1.pdf 目前未授權公開取用 | 5.72 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。