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標題: | 應用於無線通訊之連續時間三角積分調變器設計 Design of Continuous-Time Delta-Sigma Modulators for Wireless Applications |
作者: | Chan-Hsiang Weng 翁展翔 |
指導教授: | 林宗賢(Tsung-Hsien Lin) |
關鍵字: | 三角積分,類比數為轉換器,延遲迴路, delta sigma,ADC,excess loop delay, |
出版年 : | 2008 |
學位: | 碩士 |
摘要: | 在論文的第一部份,實現一個雙模連續時間三角積分調變器,可以應用於低通以及帶通兩種通訊規格,此三角積分調變器以台積電0.13微米互補式金氧半製程所實現,取樣頻率為60MHz,訊號頻寬為1MHz,中心頻率則座落於~0MHz(低通),以及2MHz(帶通),在此調變器中提出了一個滑動量化器的概念,有效地減少比較器使用的數量,達到低功率消耗的目的,供應電源為1.2伏時,需消耗約2毫瓦的功率。
在論文的第二部分,提出了一個應用於寬頻的三角積分調變器,實現架構以二階、多位元的連續時間三角積分調變器,在此調變器中,為了補償三角積分調變器操作在高速所造成的迴路延遲,在調變器中加入了被動電路補償此一迴路延遲,使系統趨於穩定的狀態,不會因為迴路的延遲造成系統極零點的移動,最終導致整體系統的不穩定,此三角積分調變器使用台積電0.13微米互補式金氧半製程所實現,其使用500MHz的取樣頻率在15MHz的頻寬下可以得到36dB的訊號雜訊比和38dB的動態範圍,使用1.2伏的供應電源時,需要消耗36毫瓦的功率。此連續時間三角積分調變器適合使用於無線接收機系統之中。 In the first work, a dual-mode second-order continuous-time delta-sigma ADC is designed and implemented. In order to achieve low-voltage, and low-power design, the sliding quantizer is implemented to save the number of the comparator. The resonator is also included to adjust the center frequency of the signal to achieve low-pass and band-pass operation. This modulator is implemented in the TSMC 0.13-μm COMS process. The simulated peak SNR of the proposed modulator achieves more than 60-dB with 1-MHz bandwidth at a 60-MHz sampling rate. The center frequency is about 0 MHz (low-pass mode) and 2 MHz (band-pass mode). The implemented modulator consumes 2 mW from a 1.2-V supply. Designed for a wide-band application, a second-order multi-bit continuous-time delta-sigma modulator is presented in the second part of this thesis. In the modulator, in order to compensate for the excess loop delay, a passive compensation technique is proposed. The additional compensation path in the modulator can compensate for the movement of poles and zeros that caused by excess loop delay. The fast compensation circuits stabilize the system when the modulator operates in high speed state. This delta-sigma modulator is implemented in the TSMC 0.13-μm COMS process. The proposed modulator achieves a 36-dB peak SNR with a 15-MHz bandwidth at a 500-MHz sampling rate and has a 38-dB dynamic range. The implemented modulator consumes 36 mW from a 1.2-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless wideband systems. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27262 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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