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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭斯彥 | |
dc.contributor.author | Wei-Hung Sun | en |
dc.contributor.author | 孫維宏 | zh_TW |
dc.date.accessioned | 2021-06-08T07:29:14Z | - |
dc.date.copyright | 2008-07-16 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-07-03 | |
dc.identifier.citation | [1] Information technology coding of moving pictures and associated audio for digital storage
media at up to about 1.5 Mbit/s. ISO/IEC 11172(MPEG-1), 1993. [2] 'Generic Coding of Moving Pictures and Associated Audio Information - Part 2: Video,'. ITU-T and ISO/IEC JTC 1, ITU-T Recommendation H.262 and ISO/IEC 13 818-2 (MPEG-2), 2003. [3] 'Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Speci cation (ITU-T Rec. H. 264| ISO/IEC 14496-10 AVC)'. in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050), 2003. [4] I. E. G. Richardson, H.264 and MPEG-4 Video Compression. John Wiley & Sons, Ltd, 2003. [5] ThomasWiegand, Overview of the h.264/avc video coding standard,' IEEE Trans. Cir- cuits Syst. Video Technol., vol. 13, p. 560, JULY, 2003. [6] G. J. S. Ajay Luthra and T. Wiegand, Introduction to the special issue on the h.264/avc video coding standard,' IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 557 { 559, 2003. [7] Intel overview of new instructions and extensions.' http://developer.intel.com/. [8] programming models.' http://www.tommesani.com/Docs.html. [9] Compiler support for the mmx, sse, and sse2 intrinsics.' http://msdn.microsoft.com/en- us/library/01fth20w.aspx. [10] K. D. J. B. Sergio Saponara, Carolina Blanch, The jvt advanced video coding stan- dard:complexity and performance analysis on a tool-by-tool basis,' [11] I. E. G. Richardson, Video Codec Design. John Wiley & Sons, Ltd, 2002. 37 [12] J. L. G. B. a. M. K. Peter List, Anthony Joch, Adaptive deblocking lter,' IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 614{619, JULY 2003. [13] D. Wu, Fast intermode decision in h.264/avc video coding,' IEEE Trans. Circuits Syst. Video Technol., vol. 15, p. 953, JULY, 2005. [14] M. Wien, Variable block-size transforms for h.264/avc,' IEEE Trans. Circuits Syst. Video Technol., vol. 13, p. 604, 2003. [15] G. Bjntegaard and K. Lillevold, Context-adaptive vlc (cvlc) coding of coe cients,' Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, May, 2002. [16] M. Horowitz, H.264/avc baseline pro le decoder complexity analysis,' IEEE Trans. Cir- cuits Syst. Video Technol., vol. 13, p. 704, 2003. [17] Mmx technology.' http://msdn.microsoft.com/en-us/library/698bxz2w.aspx. [18] Streaming simd extensions (sse).' http://msdn.microsoft.com/en- us/library/t467de55.aspx. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26858 | - |
dc.description.abstract | 多媒體與其應用在近年受到相當的推廣,而相關的技術也越來越受到重視,H.264為目前壓縮率最高的視訊壓縮標準之一,這個標準是ISO/IEC以及ITU-T兩個組織於2001年組成聯合影像團隊(JVT)並於2003年所共同發展的,由於它採用了許多和過去不同的技術,如不同區塊大小之移動評估,因此使得其壓縮效能得以再次提升,未來極有可能取代目前的MPEG1/2/4等標準,對Blue-Ray DVD、DVB-H、Digital Camcorder…等多媒體產品應用而言,是非常重要的關鍵技術。
在H.264效能提升上,我們首先以組合語言加快解碼的速度,針對每個解碼單元,使用不同的加速方式,同時減少記憶體使用與運算量,期能提高H.264的效能,可用在具有軟體開發平台的產品上,有效地提高效能並降低成本。 本篇論文針對新一代的視訊壓縮標準H.264/AVC,在baseline profile的架構規範下所支援的編解碼工具,以軟體實現一即時的解碼器,其中包含大部分需要複雜運算的解碼單元,並對各個架構做效能提升的改善研究。 經過整合後,此解碼器可以完成H.264之baseline profile的解碼流程,並且加入SIMD的方式來加速計算,而由實驗結果得知,解碼QCIF(176x144)大小的影片,其速率為300fps,可達到預期的200fps即時解碼之目標。 | zh_TW |
dc.description.abstract | H.264 is a standard for video compression.
It is also known as MPEG-4 Part 10, or MPEG-4 AVC (for Advanced Video Coding). It is one of the latest block-oriented motion-estimation-based CODEC developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). In the work on the new H.264/AVC standard, some new technical developments have been adopted for increasing the coding efficiency, these include new new prediction design such as variable block-size motion compensation with small block size. With the advent of new video coding standard, such as H.264, has increased the computation complexity. However, the continued increases in processor performance, memory density and storage capacity have led to a blurring these distinctions and video coding applications are now implemented on a wide range of processing platforms. General-purpose platforms such as personal computer (PC) processors can achieve respectable real-time coding performance and benefit from economies of scale. In this thesis, we design and implement a real-time H.264 decoder architecture including Variable block-size motion compensation, intra prediction, inverse transform, and inverse quantization. The system can decode a QCIF video in 300 fps. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:29:14Z (GMT). No. of bitstreams: 1 ntu-97-R94944028-1.pdf: 9697678 bytes, checksum: 05732afb624729266cac5ef492a6ad6b (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 H.264 Profiles and Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Video format in H.264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Coding Mode in H.264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 SIMD Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 BACKGROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Coding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Motion Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Block Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 SAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Motion Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Motion Vector Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Transform and Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.1 Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 ARCHITECTURE of the H.264 DECODER . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Motion Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Transform and Inverse Transform . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Quantization and Inverse Quantization . . . . . . . . . . . . . . . . . . . . . . . 27 4 SYSTEM IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 Structure of System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.1 NAL decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2 Slice Data decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.3 Inter Frame Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.1 Compare with JM Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 35 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 | |
dc.language.iso | en | |
dc.title | H.264即時解碼器之設計與實作 | zh_TW |
dc.title | Design and Implementation of a Real-Time H.264 Decoder | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 雷欽隆,顏嗣鈞,袁世一,呂學坤 | |
dc.subject.keyword | 編碼, | zh_TW |
dc.subject.keyword | decode, | en |
dc.relation.page | 42 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-07-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
顯示於系所單位: | 資訊網路與多媒體研究所 |
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