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標題: | 抗噪性數位互補金氧半導體電路之設計與實現 Design and Implementation of Noise-Tolerant Digital CMOS Circuits |
作者: | I-Chyn Wey 魏一勤 |
指導教授: | 吳安宇(An-Yeu Wu) |
關鍵字: | 抗噪性,馬可夫亂數場,低硬體成本,主從式的馬可夫對應,具隔離雜訊干擾機制的抗噪技術,具緩解訊號競爭的電荷維持器, noise-tolerant,Markov random field,cost-efficient,master-and-slave MRF mapping,isolated noise-tolerant technique,contention-relaxed keeper, |
出版年 : | 2008 |
學位: | 博士 |
摘要: | 雜訊干擾是超低電壓電路中的主要設計挑戰。在本論文中,我們提出四個抗噪電路技術來提升數位互補金氧半導體電路的抗噪能力,包括以馬可夫亂數場架構為基礎設計的抗噪電路、低硬體成本的馬可夫亂數場抗噪電路、具隔離雜訊干擾機制的抗噪動態電路、具緩解訊號競爭的電荷維持器之抗噪動態電路設計。
在靜態電路中,我們使用以機率為基礎的馬可夫亂數場理論來處理雜訊訊號。我們利用區域網路對應的方法來實現8位元的馬可夫亂數場抗噪前瞻進位加法器,這是第一個證實馬可夫亂數場理論在電路中抗噪效能的晶片。在聯電0.18µm製程,我們所設計的馬可夫亂數場抗噪前瞻進位加法器在10.6dB信噪比下,可達到2.88*10-6位元錯誤率的抗噪效能,且在工作電壓0.45V時,僅消耗8µw/MHz的能量。在低硬體成本的馬可夫亂數場抗噪電路中,我們提出主從式的馬可夫對應以及主從式的馬可夫邏輯電路建構方式來實現8位元的馬可夫亂數場抗噪前瞻進位加法器。在台積電0.13µm製程,低硬體成本的馬可夫亂數場抗噪前瞻進位加法器在10.6dB信噪比下,可達到7.00*10-5位元錯誤率的抗噪效能,且較直接對應實現的馬可夫抗噪性電路省下42%的電晶體數目。 在動態電路中,我們提出具隔離雜訊干擾機制的抗噪技術和以訊號感知電荷維持器為基礎之抗噪技術來提升動態電路的抗噪能力。在具隔離雜訊干擾機制的抗噪技術中,我們提出一個可以隔離雜訊干擾的機制。模擬結果顯示我們所設計具隔離雜訊干擾機制的抗噪8位元曼徹斯特加法器可以提升1.66倍的雜訊容忍能量。而且,在台積電0.18µm製程,低抗噪比的環境下,我們的設計較雙電晶體抗噪性設計節省34%的功率延遲乘積。其次,在具緩解訊號競爭的電荷維持器之抗噪設計中,我們在緩解訊號競爭的情形下避免電路節點浮接,可以更有效率地提升動態電路的抗噪能力。而且,在具緩解訊號競爭的電荷維持器的抗噪動態電路中,提升抗噪能力所需付出的效能損失可大幅降低。我們把具緩解訊號競爭的電荷維持器的抗噪32位元動態KS加法器實現於台積電0.13µm製程中。模擬結果顯示具緩解訊號競爭的電荷維持器的抗雜訊設計可以較傳統動態電路提升2.8倍的雜訊容忍能量,而且僅增加11%的晶片面積。相對地,雙電晶體抗噪設計需增加54%的面積付出。 Noise fluctuation is one of the major challenges in ultra-low power circuit design. In this dissertation, we propose four noise-tolerant techniques to enhance the noise-immunity in digital CMOS circuits, which include practical Markov Random Field (MRF) architecture mapping, cost-efficient MRF circuit design, Isolated Noise-Tolerant (INT) Technique, and Contention-Relaxed Keeper (CRK) designs. In static CMOS circuits, we apply a probabilistic-based approach based on the MRF theory to cope with the noisy signals. To demonstrate the proof-of-concept design, we implemented the world-first silicon-proven MRF chip, an MRF 8-bit carry-lookahead adder, by the proposed MRF local network mapping. With 0.18µm CMOS technology, the MRF_CLA can achieve 2.88*10-6 bit-error-rate (BER) under 10.6dB SNR and its energy consumption is only 8µw/MHz under 0.45V supply voltage. In the cost-efficient MRF design, we design and implement an 8-bit MRF_CLA, based on master-and-slave MRF mapping and master-and-slave MRF logic gate construction. The proposed master-and-slave MRF_CLA can provide 7.00*10-5 BER under 10.6dB SNR and its transistor count can be saved by 42% as compared with the direct-mapping MRF design. In dynamic CMOS circuits, we propose the INT and CRK techniques to enhance the noise-immunity. In the INT design, we propose a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66X average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18μm process. In the CRK design, it can prevent the dynamic node from floating in a contention-relaxed manner. Therefore, it can enhance the noise tolerance of dynamic circuits more effectively. Moreover, in the proposed CRK design, the performance overhead for enhancing the noise-tolerance can be greatly reduced. We apply the proposed CRK technique to the 32-bit KS adder circuit under TSMC 0.13um process. Simulation results show that the CRK design can provide 2.8X ANTE as compared with the conventional domino design. Moreover, the area overhead in the proposed design is only 11%, whereas area overhead in the twin-transistor technique is 54%. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26856 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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