請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26793完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Fai-Pei Lai) | |
| dc.contributor.author | Chung-Ping Tan | en |
| dc.contributor.author | 譚仲平 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:25:54Z | - |
| dc.date.copyright | 2008-07-23 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-14 | |
| dc.identifier.citation | [1] Kiyoo Itoh “VLSI Memory Chip Design” Itoh, Kiyoo, 1941-
Berlin ; New York : Springer, c2001 [2] Fang-shi Lai and Chia-Fu Lee ”On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology”. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 [3] Chua-Chin Wang, Ching-Li Lee, and Wun-Ji Lin “A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme”. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 5, MAY 2007 [4] Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, andShuhei Iwade, “A 90-nm Low-Power 32-kB Embedded SRAM With Gate LeakageSuppression Circuit for Mobile Applications”. IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 39, NO. 4, APRIL 2004 [5] K. Nii, et al. “A low power SRAM using auto-backgate-controlled MT-CMOS”. In International Symposium on Low Power Electronics and Design, pp.293-298m 1998. [6] K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits”. In Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. [7] International Technology Roadmap for Semiconductors, 2001 Update, Semiconductors Industry Assoc. and SEMATECH. [8] A. Chandrakasan. “Low power circuit and system design”, 2000. International Electron Device Meeting. [9] K. Flautner, et al. “Drowsy Caches: Simple Techniques for Reducing Leakage Power”. In The 29th Annual International Symposium on Computer Architecture, pp. 148-157, May 2002. [10] M. Powell, et al. “Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories”. In International Symposium on Low Power Electronics and Design, pp.90-95, 2000. [11] M. Horiguchi, T. Sakata, and K. Itoh, “Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSIs,” in Symp. VLSI Circuits Dig., 1993, pp. 47–48. [12] H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, and K. Uchiyama, “An 18-uA standby current 1.8-V 200-MHz microprocessor with self-substrate-biased data-retention mode,” IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1492–1500, Nov. 1999. [13] K. Noda, K. Matsui, K. Takeda, and N. Nakamura, “A loadless CMOS four-transistor SRAM cell in a 0.18 um logic technology,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2851–2856, Dec. 2001. [14] J. Wu and K. Chang, “MOS Charge Pumps for Low-Voltage Operation,” IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592-597, April 1998. [15] K. Phang., “CMOS Optical Preamplifier Design Using Graphical Circuit Analysis,” Ph.D. Thesis, University of Toronto, 2001 [16] Hiroki Morimura and Nobutaro Shibata, “A Step-Down Boosted Wordline Scheme for 1-V Battery-Operated Fast SRAM’s” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998 [17] Eiji Morifuji, Dinesh Patil, and Mark Horowitz, “Power Optimization for SRAM and Its Scaling” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 4, APRIL 2007 [18] Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, “A Low-Power Four-Transistor SRAM Cell With a Stacked Vertical Poly-Silicon PMOS and a Dual-Word-Voltage Scheme” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005 [19] Kenji Noda, Koujirou Matsui, Koichi Takeda, and Noritsugu Nakamura, “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18um Logic Technology” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001 [20] Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Member, IEEE, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, and Hiroyuki Takahashi “A 16-Mb 400-MHz Loadless CMOS Four-Transistor SRAM Macro ”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 11, NOVEMBER 2000 [21] L. Dongwoo, D. Blaauw, D. Sylvester, 'Gate oxide leakage current analysis and reduction for VLSI circuits', Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, Vol. 12, No. 2, Feb. 2004, pp. 55 - 166. [22] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, 'Leakage current mechanisms and leakage reduction techniques in deep-sub micrometer CMOS circuits', IEEE, Vol. 91, No. 2, Feb. 2003, pp. 305 - 327. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26793 | - |
| dc.description.abstract | 靜態隨機存取記憶體被廣泛應用在像是電腦中多核心中央運處理單元的第二級快取記憶體，高速交換器，路由器和高速網路伺服器的第三級快取記憶體等許多高速運算相關的緩衝存取記憶工作。以及液晶平面顯示器中驅動IC，系統單晶片及手機系統中的嵌入式應用。因為有著高速工作時脈和小型存取容量及較小的晶片面積等優點可以達到高度彈性與各種眾多整合性產品的系統應用。
雖然六電晶體的記憶體單元被廣泛的使用在各種靜態記憶體電路中，但是因為先天上的架構造成需要佔據較大的晶片單位面積與功率消耗，為了達成小面積與低功耗低成本的設計，本論文中將採用四個電晶體的架構來組成記憶體單元。導因於半導體製程的演進，使得次微米正式進入到深次微米製程後，互補式金氧半電晶體元件的漏電流問題日趨嚴重，靜態功率消耗的設計與考量也成為了記憶體中一個重要的課題，本論文將利用負字元線的方法來抑制在次微米製程中的靜態次臨界漏電流而不使用任何特別的多臨界電壓製程。再藉由電壓幫浦稍稍增加一些電路消耗功率，換取瞬間提高記憶體單元中的供給電壓以得到更高的靜態雜訊邊限。同時，為了要有更高的系統整合度以及更符合低成本的大量製造原則，將採用互補式金氧半導體製程來設計與模擬，以期能設計出高效能且低功耗的靜態隨機存取記憶電路。 本論文將提出一個記憶容量大小為1k，以四電晶體為記憶單元的低功耗靜態記憶體電路，利用電壓幫浦在資料讀取時瞬間，提高記憶單元供給電壓，來有效改善靜態雜訊邊限，並採用負字元線，來縮小記憶體電路在靜態待命時的閘極漏電流。最後，將會提出一個雙端輸入單端輸出，利用電流轉換電壓的電流感應放大器，並在單端輸出後方加上史密特觸發器，來幫助抑制位元線上的雜訊。本論文中所有電路均以台積電0.18微米互補式金氧半導體製程來設計與模擬，儲存大小為1k，靜態雜訊邊限為530毫伏特，靜態漏電流為0.082毫安培，電路功率消耗在待命，讀取與寫入分別為0.18毫瓦，9.43毫瓦與7.38毫瓦。 | zh_TW |
| dc.description.abstract | Static random access memory (SRAM) has its own name known loud and clear in the hood of the high speed memory applications. From the level 2 (L2) caches in the gigahertz multi-core central processing units (CPUs), level 3 (L3) caches in the high speed switches, hubs and network servers to the embedded uses such as the liquid crystal display (LCD) driver ICs, system-on-a-chips (SoCs) and cell phone integrations, SRAM works all. It aims to the field of the high speed data rate use in a rather smaller memory size in both memory capacity and die area with full of the flexibility and integrability.
Despite the mostly adopted 6-T memory cell is so classic and seemingly flawless. When talking of the necessarily active area issue then is another story. Less is more, hence we assume the 4-T cell to be the memory core of our design. With the aid of the negative word line scheme, the dramatically increased sub-threshold leakage in the sub-micron technology is then effectively eliminated without using any special process fabrication technology. As to noise, boosting the cell supply voltage gains us a significantly static noise margin (SNM) improved with a little extra power penalty. Meanwhile, the CMOS technology is the chosen one for us with the higher-level system integration and lower-cost manufacturing requirement. Looking forward to be in the way of making it powerful but not power hungry. In this thesis, we propose a SNM improved, low power consumption 1k 4-T SRAM structure with the boosted cell power supply by the proposing voltage heap pump, and the negative word line scheme in order to minimize the stand-by gate leakage current. Further, by proposing a current to voltage type current sense amplifier with Schmitt trigger adds a little help to fight for the noise interference. Simulated in the TSMC 0.18um CMOS process, the SNM of this 1k SRAM circuit is 530mV with the stand-by leakage current about 0.082mA, and consumes only 0.18mW, 9.43mW and 7.38mW in stand-by, read and write, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:25:54Z (GMT). No. of bitstreams: 1 ntu-97-J93921038-1.pdf: 5039033 bytes, checksum: c093e9db42b52141da48e1cbde816b17 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Overview 3 Chapter 2 The Essentials of Static Random Access Memory 6 2.1 The Memory Classification……………………………………….6 2.2 The SRAM Building Blocks…..………………………………….7 2.2.1 The Memory Core 9 2.2.2 The Address Decoders 9 2.2.3 Sense Amplifiers 12 2.3 Operating Principles………..……………………………………13 2.3.1 Data Reading 14 2.3.2 Data Writing 14 2.3.3 Data Retention 15 2.4 Noise Sources in SRAM 16 2.4.1 Signal-to-Noise Ratio 16 2.4.2 Bitline-to-Bitline Coupling 17 2.4.3 Wordline-to-Bitline Coupling 18 2.4.4 Leakage 19 2.5 Power Dissipation 21 2.5.1 Partitioning 21 2.5.2 Active Power Reduction 22 2.5.3 Power Dissipation of Data Retention 22 Chapter 3 SRAM with Negative Word-line Scheme 25 3.1 Related Works in Leakage Suppression 25 3.1.1 MT-CMOS 26 3.1.2 Drowsy Cache 27 3.1.3 Gated-VDD 28 3.2 Leakage Mechinasm……………………………………………..30 3.2.1 Leakage Sources in the CMOS Technology………………30 3.2.2 Main Leakage Sources in the Sub-micron And Deep Sub-micron CMOS Technology…………………………. 36 3.3 Low Leakage SRAM Design 36 3.3.1 4T Memory Cell 36 3.3.2 NMOS vs. PMOS Leakage 37 3.3.3 Two Types of 4T SRAM Cell 37 3.4 Model Analysis On Sizing Constraint 38 3.4.1 Read Operation 39 3.4.2 Writing Operation 40 3.4.3 Stored Data Under Leakage 42 3.5 Negative Voltage Scheme 42 3.5.1 Negative Bulk 42 3.5.2 Negative Wordline 43 3.5.3 Comparison 44 3.6 Summary 45 Chapter 4 Heap Pump Based Dynamic Power Supply 47 4.1 Related Works in the Dynamic Power Supply 47 4.1.1 Voltage Down Converter 48 4.1.2 Local DC Level Controller 48 4.2 Dynamic Power Supply 49 4.2.1 Analysis of SNM Improvement 50 4.3 Charge Pump Basics 51 4.3.1 Ideal Voltage Doubler 52 4.3.2 Practical Voltage Doubler 53 4.3.3 Basic Charge Pump 54 4.3.4 Proposed Heap Pump 55 4.4 Operating Principle 56 4.5 Simulation Result 57 4.6 Summary 58 Chapter 5 4T SRAM with Heap Pump Boosted Cell Supply Voltage and Negative Wordline 59 5.1 Architecture 59 5.1.1 4T Memory Cell 60 5.1.2 Row Decoder 61 5.1.3 Column Decoder 62 5.1.4 Current to Voltage Current Sense Amplifier 63 5.1.5 Voltage Heap Pump 65 5.1.6 Write Control 65 5.1.7 Predischarger 67 5.2 Operating Principle 68 5.2.1 Read Operation 68 5.2.2 Write Operation 69 5.2.3 Stand-By Operation 70 5.3 Simulation Results 70 5.3.1 Cell Leakage Power 70 5.3.2 Decoders 71 5.3.3 Predischarger 72 5.3.4 Write Control 72 5.3.5 Heap Pump Boosted Supply Voltage 73 5.3.6 Current Sense Amplifier 74 5.3.7 Read/Write/Stand-by Operation 74 5.3.8 Static Noise Margin 76 5.3.9 Power Consumption 78 5.4 Summary 79 Chapter 6 Conclusion 81 Bibliography 82 | |
| dc.language.iso | en | |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 靜態隨機存取記憶體 | zh_TW |
| dc.subject | 電壓幫浦 | zh_TW |
| dc.subject | Heap Pump | en |
| dc.subject | Low Power | en |
| dc.subject | SRAM | en |
| dc.title | 利用電壓幫浦提升四電晶體記憶單元供壓與負字元線的低功耗靜態隨機存取記憶體 | zh_TW |
| dc.title | Low Power 4T SRAM with Heap Pump BoostedCell Supply Voltage and Negative Word Line | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張延任,蔡坤霖,李鴻璋,張孟洲 | |
| dc.subject.keyword | 靜態隨機存取記憶體,電壓幫浦,低功耗, | zh_TW |
| dc.subject.keyword | SRAM,Heap Pump,Low Power, | en |
| dc.relation.page | 84 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-97-1.pdf 未授權公開取用 | 4.92 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。