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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為(Chee-Wee Liu) | |
dc.contributor.author | Chia-Ting Cho | en |
dc.contributor.author | 卓佳錠 | zh_TW |
dc.date.accessioned | 2021-06-08T07:22:06Z | - |
dc.date.copyright | 2008-07-24 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2008-07-22 | |
dc.identifier.citation | [1] H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” IEDM Tech. Dig., 157, 1989
[2] N. Ibaraki,” Low-Temperature Ply-Si TFT Technology” SID Symposium Digest, Vol.30, pp.172-175, 1999. [3] B. Lee et al., “A CPU on a Glass Substrate Using CG-Silicon TFTs,” ISSCC Digest of Technical Papers, pp. 164-165, 2003 [4] Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Tsuchihashi, “Reliability of high-frequency operation of low-temperature polysilicon thin film transistors under dynamic stress,” Jpn. J. Appl. Phys., vol. 39, pp. L1209–L1212, 2000. [5] T. W. Little, K. I. Takahara, H. Koike, et al, “Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical vapor deposition gate insulator”, Jpn. J. Appl., Phys., vol.30, no.12B, pp.3724-3728,December 1991. [6] Hiroyuki Kuriyama, Seiichi Kiyama, Shigeru Nouguchi, et al, “Enlargement of poly-Si Film Grain Size by Excimer Laser Annealing and its Application to High-Performance Poly-Si Thin Film Transistor”, Jpn. J. Appl. Phys., vol.30, no.12B, pp.3700-3703, December 1991. [7] S. W. Lee and S.K. Joo, “Low Temperature Poly-Si Thin Film Transistors Fabrication by Metal-Induced Lateral Crystallization”, IEEE ElectronDevice Lett., vol.17, no4, pp.160-162, April 1996. [8] J. B. Boyce and P. Mei, “Laser crystallization for polycrystalline silicon device applications,” in Technology and Application of Amorphous Silicon, R. A. Street, Ed. New York: Springer-Verlag, pp.94-146, 2000. [9] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982. [10] P. Migliorato, C. Reita, G. Tallarida, M. Quinn and G. Fortunato,” Anomalous Off-Current Mechanisms in N-Channel Poly-Si Thin Film Transistors.” Solid-State-Electronics, Vol.38, No.12, pp.2075-2079, 1995. [11] M. Hack, I-W. Wu, T. J. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,”IEDM Tech Dig., Vol. 93, pp.385-388,December 1993. [12] J.Y. Seto J. Appl. Phys. 46 (1975), p. 5242. [13] Ted Kamins, “Polycrystalline silicon for integrated circuits and displays”, second edition. [14] RR Troutman, ‘‘VLSI limitations from drain-induced barrier lowering,’’ IEEE J. Solid-State Circuits, vol. SC-14, pp. 383, 1979. [15] C.-F. Huang et al., International Semiconductor Device Research Symposium (ISDRS), Washington D.C., December, 2007. [16] Mansun Chan, et al, “A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation”, IEEE Transactions on Electron Devices, Volume: 45 , Issue: 4 , April 1998 pp:834 – 841 [17] ISE TCAD Release 10.0, part 15, “Dessis”, pp:15.527- 15.527 [18] Y. Okuto and C. R. Crowell, “Threshold energy effects on avalanche breakdown voltage in semiconductor junctions,” Solid-State Electronics, vol. 18, pp. 161–168, 1975. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26713 | - |
dc.description.abstract | 近年來低溫多晶矽薄膜電晶體在平面顯示器驅動電路中廣為使用,利
用準分子雷射結晶法可將非晶矽玻璃基板上重新結晶為多晶矽,藉以提高 載子移動率,使達到先進顯示技術,更進一步達到系統整合於玻璃基板的 目的。元件的穩定性及可靠度是決定產品良率的重要因素,因此在本論文 中將針對多晶矽薄膜電晶體之可靠度進行研究。 在第二章中,將介紹低溫多晶矽電晶體的基本特性,包括準分子電射 回火法和晶粒邊界,接著利用模擬軟體改變元件中輕摻雜汲極的長度,以 研究其長度與汲極引發能障降低效應之關係 第三章研究低溫多晶矽薄膜電晶體在交流電壓下的劣化效應。根據實 驗結果,其劣化效應程度與其正負偏壓、偏壓大小以及頻率有關。其機制 可以用衝擊游離解釋,在靠近源極和汲極之區域,衝擊游離產生新的電子 電洞對並破壞晶粒邊界的矽氫鍵結。 第四章用模擬軟體進行暫態分析來研究衝擊游離在p 通道如何運作。 我們做了電流分析以及能帶分析,發現在正極性與負極性的電壓應力下有 不同的機制。在負極性的時候,通道會因電洞從源極及汲極注入而馬上變 成反轉型態,所以不會造成元件的劣化。而在正極性的時候,因為無法在 表面產生電子,閘極所施加的偏壓會落在通道及源極(汲極)間並產生衝擊 游離。 | zh_TW |
dc.description.abstract | In recent years, low temperature polycrystalline silicon thin film transistors
(LTPS TFTs) have been widely used in flat panel display driving circuit. By excimer laser crystalline method, high quality of p-Si can be produced on the glass substrate at low temperature with high mobility to advanced display, which leads to system-on-glass (SOG). Stability and reliability are important factors to determine product yield, so this thesis would investigate the reliability of poly-Si TFTs. Chapter two would introduce basic characteristics of LTPS TFTs, including excimer laser annealing (ELA) method and grain boundary, following by device of simulation, which changes the length of lightly-doped-drain (LDD) region in the structure, to study the extent of drain-induced barrier lowering (DIBL). Chapter three investigates the degradation effect of LTPS TFTs under dynamic stress through experiment. According to experiment results, the degradation extent is linked to the polarity of bias stress, stress amplitude and frequency. The mechanism could be explained by impact ionization, which causes the electron scattering into insulator and hot carriers breaking Si-H bonds at interface and grain boundary around S/D region. Chapter four performs transient analysis by simulator to investigate how the VII impact ionization operates in p-channel TFTs. We simulate current analysis and band diagram analysis, and discover difference mechanisms in positive and negative polarities. In negative polarity, channel would immediately become inversion due to hole injection from source/drain (S/D) and no degradation occurs. In positive polarity, no electrons are generated in the channel surface, and the gate bias stress would drop between channel and S/D, which results in impact ionization. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:22:06Z (GMT). No. of bitstreams: 1 ntu-96-R95941009-1.pdf: 449517 bytes, checksum: 549fbb3bb291a0a3f03ea34c83cd977f (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | Contents
List of Figures ......................................................................... X List of Tables ........................................................................ XIII Chapter 1 Introduction 1.1 Motivation................................................................................................1 1.2 Thesis organization ..................................................................................2 References............................................................................................................4 Chapter 2 Fundamentals of Poly-Si TFT and DIBL effect 2.1 Motivation................................................................................................5 2.2 Poly-silicon Film by Excimer Laser Crystallization Method ..................6 2.3 Grain Boundary........................................................................................9 2.4 Device Parameter Extraction .................................................................11 2.5 I-V Measurement and Dynamic Stress ..................................................12 2.6 Concept of Drain Induced Barrier Lowering (DIBL) ............................12 2.7 Simulation and Discussion of the Results..............................................13 2.8 Summary ................................................................................................14 References..........................................................................................................21 Chapter 3 LTPS TFTs under dynamic stress 3.1 Introduction............................................................................................22 3.2 Experiment Procedure............................................................................23 3.3 Results and Discussion ..........................................................................24 3.4 Summary ................................................................................................27 References..........................................................................................................35 Chapter 4 Transient analysis of LTPS TFTs 4.1 Introduction............................................................................................36 4.2 Model Description .................................................................................37 IX 4.2.1 Transient Model ............................................................................37 4.2.2 Impact Ionization Model...............................................................38 4.3 Simulation Results and Discussion........................................................40 4.3.1 Negative Polarity ..........................................................................40 4.3.2 Positive Polarity............................................................................41 4.3.2.1 Rising Time and Positive DC stress...................................41 4.3.2.2 Falling Time .......................................................................43 4.3.2.3 Transient Current ...............................................................44 4.3.3 Full Cycle Stress ...........................................................................46 4.4 Summary ................................................................................................47 References..........................................................................................................60 Chapter 5 Summary and Future Work 5.1 Summary ................................................................................................61 5.2 Future Work ...........................................................................................62 | |
dc.language.iso | en | |
dc.title | 薄膜電晶體可靠度之研究 | zh_TW |
dc.title | Investigation on Reliability of Thin-Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李勝偉(Sheng-Wei Lee),李敏鴻(Min-Hung Lee),林中一(Chung-Yi Lin),許晉瑋(Jin-Wei Shi) | |
dc.subject.keyword | 薄膜電晶體,準分子雷射結晶法,輕摻雜汲極,汲極引發能障降低,衝擊游離, | zh_TW |
dc.subject.keyword | thin film transistors,excimer laser crystalline method,lightly-doped-drain,drain-induced barrier lowering,impact ionization, | en |
dc.relation.page | 62 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-07-24 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
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