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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為 | |
dc.contributor.author | Che-Yung Lin | en |
dc.contributor.author | 林哲永 | zh_TW |
dc.date.accessioned | 2021-06-08T07:21:43Z | - |
dc.date.copyright | 2008-07-24 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-07-24 | |
dc.identifier.citation | [1] A. Luque and S. Hegedus, “Handbook of Photovoltaic Science and Engineering”
(Wiley, 2003). [1] Guillermo Gonzalez, “MICROWAVE TRANSISTOR AMPLIFIER Analysis and Design Second Edition”. [2] M. Kumar, Y. Tan, J. K. O. Sin, “Excellent Cross-Talk Isolation, High-Q Inductors, and Reduced Self-Heating in a TFSOI Technology for System-on-a-Chip Applications,” IEEE Trans. Electron Devices, vol. 49, no. 4 pp. 84-589, April 2002. [3] J. H. Mikkelsen, O. K. Jensen, and T Larsen, “Crosstalk coupling effects of CMOS co-planar spiral inductors,” IEEE Custom Integrated Circuit Conference (CICC), pp. 371-374, 2004. [4] C. S. Kim, P. Park, J.-W. Park, N. Hwang, and H. K. Yu, ”Deep trench Guard Technology to Suppress Coupling between Inductors in Silicon RF ICs,” IEEE MTT-S Symp. Dig., pp. 1873-1876, June 2001. [5] H. –S. Kim, K. A. Jenkins, and Y. –H. Xie, “Effective Crosstalk Isolation Through P+ Si Substrate with Semi-Insulating Porous Si,” IEEE Electron Device Lett., vol. 23, no. 3, pp. 160-162, March 2002. [6] Y. H. Wu, A. Chin, K. H. Shih, C. C. Wu, C. P. Liao, S. C. Pai, and C. C. Chi, ”Fabrication of Very High Resistivity Si with Low Loss and Cross Talk,” IEEE Electron Device Lett., vol. 21, no. 9, pp. 442-444, September 2000. [1] A. Luque and S. Hegedus, “Handbook of Photovoltaic Science and Engineering” (Wiley, 2003). [2] DeJule R, “Semiconductor International” (Nov. 1988). [3] Auberton-Herve A et al., Proc. 2nd International Symposium on Advanced Science and Technology of Silicon Materials, 214 (Kona, Hawaii, Nov. 1996). [4] Jasprit Singh, “Semiconductor Devices” (McGraw-Hill). [5] M. B. Prince, “Silicon Solar Energy Converters” J. Appl. Phys., 26, 534 (1955). [6] S. M. Sze, “Physics of Semiconductor Devices” (Wiley, New York, 1981). [7] C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo and B. C. Hsu, “IEEE Electron Device Lett. 21” (2000). [1] A. Luque and S. Hegedus, “Handbook of Photovoltaic Science and Engineering” (Wiley, 2003). [2] DeJule R, “Semiconductor International” (Nov. 1988). [3] Auberton-Herve A et al., Proc. 2nd International Symposium on Advanced Science and Technology of Silicon Materials, 214 (Kona, Hawaii, Nov. 1996). [4] Jasprit Singh, “Semiconductor Devices” (McGraw-Hill). [5] M. B. Prince, “Silicon Solar Energy Converters” J. Appl. Phys., 26, 534 (1955). [6] S. M. Sze, “Physics of Semiconductor Devices” (Wiley, New York, 1981). [7] C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo and B. C. Hsu, “IEEE Electron Device Lett. 21” (2000). | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26705 | - |
dc.description.abstract | 在本論文中,首先將介紹用於雙功率放大器間的隔離技術。對於雙功率放大器隔離度而言,在經過第一次的雷射切割後等效的耦合效應量為-27.2dB,經過第二次雷射切割後等效的耦合效應量為-29.25dB,只開啟上半部功率放大器、上下部功率放大器同時開啟及下半部功率放大器輸入功率大於上半部10dBm時的第一次雷射切割後所量得的EVM分別為11.4dBm、8.9dBm及7.8dBm,而經過第二次雷射切割後的EVM分別為15dBm、13.9dBm及9.8dBm。若操作在單一功率放大器時,其線性增益為18.6dB,1dB壓縮點功率為25.3dBm,壓縮點增加效益為16.7%。其次,使用ISE軟體來進行太陽能電池特性的模擬。利用量測商用太陽能電池的電性特性來建立ISE模擬中的模型,並針對參雜濃度、電極寬度及間距、奈米級表面結構來進行太陽能效率的最佳化模擬。 | zh_TW |
dc.description.abstract | In this thesis, an isolation technique for dual power amplifiers is introduced. For the isolation of dual power amplifiers, the equivalent coupling effect at 2.45GHz before laser cut is -24.7dB, after first laser cut is -27.2dB and after second laser cut is -29.25dB. The EVM at 3% criterion after first laser cut of standalone condition is 11.4dBm, of equal power is 8.9dBm and of 10dB larger input power from down-PA is 7.8dBm. After second laser cut the EVM at 3% criterion of standalone condition is 15dBm, of equal power is 13.9dBm and of 10dB larger input power from down-PA is 9.8dBm. The small signal gain, P1dB and PAE at P1dB are 18.6dB, 25.3dBm and 16.7%, respectively. By measuring electrical characteristics of commercial solar cells, the solar cell model can be established in ISE. Furthermore, the optimization simulations of doping profile, finger width and spacing and nano texture are performed. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:21:43Z (GMT). No. of bitstreams: 1 ntu-97-R95943061-1.pdf: 12650741 bytes, checksum: 66efe5978dcccc7e05e75c1bb2afeb0f (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Contents
List of Figures…………………………………………………………..VI List of Tables……………………………………………………………IX Chapter 1 Introduction 1.1 Introduction………………………………………………………………….....1 1.2 Motivation……………………………………………………………………...4 References……………………………………………………………………….....5 Chapter 2 Multiple Deep Trench Isolation and Suppression of Gain Expansion Effect of Dual Power Amplifiers 2.1 Introduction………………………………………………………………….....6 2.2 The Design of the 802.11n Power Amplifier…………………………………...7 2.2.1 Circuit Design………………………………………………………….....7 2.2.2 Active-Bias Circuit with Temperature Compensation……………………8 2.2.3 Design of Matching Network……………………………………………..9 2.2.4 λ/4 Transmission Line…………………………………………………...11 2.2.5 Circuit Layout and Isolation Technique…………………………………12 2.2.6 Wire Bonding Diagram and Complete Photo of PA Module……………14 2.2.7 Reduction of Gain Expansion…………………………………………...15 2.3 CW Measurement Results of a Single PA…………………………………….16 2.4 Small Signal Coupling Effects on S-parameter………………………………..20 2.5 Large Signal Coupling on EVM……………………………………………….23 2.6 Conclusion……………………………………………………………………..26 References…………………………………………………………………………27 Chapter 3 Si-Wafer Solar Cell Simulation 3.1 Introduction……………………………………………………………………29 3.2 Solar Spectrum and Physics of Solar Cells……………………………………30 3.3 Basic P-N Diode Device Structure…………………………………………….34 3.4 Comparison of ISE Simulation and Experiment………………………………37 3.5 External Quantum Efficiency………………………………………………….39 3.6 Bulk Lifetime and External Quantum Efficiency……………………………..40 3.7 Conclusion…………………………………………………………………….41 References…………………………………………………………………………41 Chapter 4 Efficiency Improvement and Optimization Simulation for Si-Wafer Solar Cell 4.1 Introduction…………………………………………………………………...43 4.2 Optimal Wafer Thickness……………………………………………………..43 4.3 Optimal Doping Profile……………………………………………………….45 4.4 Optimal Finger Spacing and Finger Width……………………………………50 4.5 Nano Texture Solar Cell Simulation…………………………………………..54 4.6 Conclusion…………………………………………………………………….57 References…………………………………………………………………………59 Chapter 5 Summary and Future Work 5.1 Summary………………………………………………………………………60 5.2 Future Work……………………………………………………………………62 | |
dc.language.iso | en | |
dc.title | 矽鍺功率放大器隔離技術與太陽能電池特性模擬 | zh_TW |
dc.title | Isolation Technique for SiGe Power Amplifiers
and Simulation of Solar Cell Characteristics | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李文欽,葉致宏,陳奕君,郭華軒 | |
dc.subject.keyword | 功率放大器,太陽能電池, | zh_TW |
dc.subject.keyword | SiGe,power amplifier,solar cell, | en |
dc.relation.page | 63 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-07-24 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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