使用命中線回授之低功率內容定址記憶體

Abstract

隨著積體電路和電腦系統的演進，低功率消耗的要求也跟著提高，低功率的設計不但可以減少熱能發散，同時也可延長產品的使用壽命。降低功率消耗的方法目前多半是使用降低供電電壓的方式來減少功率消耗，但是降低供電電壓會產生一些的副作用，如：抗雜訊能力下降等。 內容可定址記憶體被廣泛的應用在生活上諸如資料庫、網路路由器…等。在需要高速搜尋的應用當中，由於內容可定址記憶體是以平行比對的機制所以其具有高速的特性，但是相對的卻造成了相當高的功率消耗。 本論文提出了一個新的方法，利用從命中線回授訊號來關閉放電路徑以達到降低功率消耗。我們使用 Synopsys 公司的 HSIPCE 搭配 0.18μm 的製程檔進行模擬。根據模擬結果，相較於傳統架構，本論文提出的方法在32-bit時平均功率消耗減低了達44%，搜尋延遲拉長了16%。64-bit時平均功率消耗減低了達46%，搜尋延遲拉長了18%。128-bit時平均功率消耗減低了達47%，搜尋延遲拉長了15%。

With the evolution of VLSI and computer system, the requirement of low power consumption is enhanced too. The low power design can not only reduce the heat scatter, but also can increase the product life time. The power saving method usually used the low supply voltage to reduce power consumption, but reduce power supply voltage would have some problem, like noise immunity decreased, etc. Content addressable memory is widely used in database, routers, etc. in the applications that require high search speed, because the content addressable memory does parallel comparison so it has high speed characteristic, but result in quite high power consumption. In this thesis, we propose a new method using the feedback from matchline signal to turn off the discharge path and reduce power consumption. We further implement and simulate the whole architecture by Synopsys Hspice using 0.18μm technology. Simulation results of the 32-bit show our method has a reduction of power consumption up to 44% with a 16% longer latency in comparison of the conventional structure. When simulated in the 64-bit, the reduction of the power consumption is up to 46% with an 18% longer latency. In 128-bit, the power consumption of our method is 47% less with a 15% longer latency in comparison of the conventional structure.