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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Hung-Yu Lu | en |
| dc.contributor.author | 盧泓諭 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:19:46Z | - |
| dc.date.copyright | 2011-08-12 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-10 | |
| dc.identifier.citation | [1] S. Pamarti, L. Jansson and I. Galton, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL With 1-Mb/s In-Loop Modulation,” IEEE J. Solid-State Circuits, vol. 39, pp. 49–62, Jan. 2004.
[2] M. Gupta and B. S. Song, “A 1.8-GHz Spur-Cancelled Fraction-N Frequency Synthesizer With LMS-Based DAC Gain Calibration,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2842–2851, Mar. 2006. [3] C. M. Hsu, M. Z. Straayer and M. H. Perrot, “A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circuits, vol. 43, pp. 2776–2786, Dec. 2008. [4] I. Bietti, E. Ternporitil, G. Albasini, and R. Castello, “An UMTS SD fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @1MHz using spurs compensation and linearization techniques,” in IEEE Custom Integrated Circuits Conf., 2003, pp. 463–466. [5] X. Yu, Y. Sun, W. Rhee and Z. Wang, “An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators,” IEEE J. Solid-State Circuits, vol. 44, no. 9, Sep. 2009. [6] X. Yu, Y. Sun, W. Rhee, H. K. Ahn, B. H. Park and Z. Wang, “A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications,” IEEE J. Solid-State Circuits, vol. 44, no. 8, August 2009. [7] T. Riley, N. Filiol, Q. Du, and J. Kostamovaara, “Techniques for in-band phase noise reduction in ΔΣ synthesizers,” IEEE Trans. Circuits Syst. II, vol. 50, no. 11, pp. 794–803, Nov. 2003. [8] M. J. Borkowski and J. Kostamovaara, “Post-modulator filtering in ΔΣ fractional-N frequency synthesis,” in Proc. IEEE 47th Int. Midwest Symp. Circuits Syst., Jul. 2004, vol. 1, pp. I325–I328. [9] M. Zanuso, S. Levantino, C. Samori and A. L. Lacaita, “A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 627–638, Mar. 2011. [10] D. W. Jee, Y. Suh, H. J. Park and J. Y. Sim, “A 0.1-fref BW 1GHz Fractional-N PLL with FIREmbedded Phase-Interpolator-Based Noise Filtering,” ISSCC, pp.94-96, Dig. Tech. Papers, Feb. 2011. [11] C. S. Vaucher and D. Kasperkovitz, “A wide-band tuning system for fully integrated satellite receivers,” IEEE J. Solid-State Circuits, vol. 33, pp. 987–997, July 1998. [12] B. Razavi, “The Role of PLLs in Future Wireline Transmitters, ” IEEE Transactions on circuits and systems — I: regular paper, vol. 56, no. 8, Aug. 2009. [13] S. Y. Lee, S. Amakawa, N. Ishihara and K. Masu, “ Low-phase-noise wide-frequency-range differential ring-VCO with non-integral sub-harmonic locking in 0.18/um CMOS,” Microwave Integrated Circuits Conference (EuMIC), pp. 464-467, Sep. 2010 European [14] J. Lee and H. Wang, “Study of Subharmonic Injection-Locked PLLs,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp.1539-1553, MAY 2009. [15] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, pp.1571-1580, Sept. 2004. [16] N. D. Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52, pp.505-509, Jan., 2005. [17] V. Kratyuk, “Digital phase-locked loops for multi-GHz clock generation,” PhD Thesis, Oregon State University, Dec. 2006. [18] C. M. Hsu, 'Techniques for high-performance digital frequency synthesis and phase control,' PhD Thesis, Massachusetts Institute of Technology, Sep. 2008. [19] S. Y. Lin, and S. I. Liu, 'A 1.5GHz All-digital Spread Spectrum Clock Generator', IEEE J. Solid-State Circuits, vol. 44, pp. 3111-3119, Nov. 2009. [20] P. Dudek, S. Szczepanski, and J.V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, pp. 240–247, Feb. 2000. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26663 | - |
| dc.description.abstract | 近來，隨著越來越多傑出的研究成果，全數位鎖相迴路已然變為一個當紅的研究主題。跟傳統類比電路使用充電汞的架構相比，全數位的架構有著以下的強勢優點：容易在不同製程之間做電路轉換、小面積、先進製程的高電路成果表現以及易與數位電路系統整合等好處。為了更進一步發展全數位鎖相迴路的潛力，在本篇論文中我們完成兩個跟全數位鎖相迴路有關的架構設計。
在第一顆晶片中，一個使用嵌入式有限脈波響應濾波器的60億赫茲除小數頻率合成器的設計被提出，用以抑制傳統的除小數頻率合成器中，受限於量化雜訊的問題。其根本概念是利用調變器與振盪器的資訊，經由數位電路的運算，來補償主迴路上所產生的量化誤差，因此得以節省許多晶片面積及電功率消耗。實驗的晶片是使用台積電90奈米的互補式金氧半場效電晶體製程，量測的結果在使用所提出的演算法下，量化雜訊在輸出端的相位雜訊被壓抑了15dB，晶片中的電路面積占了0.18 mm2 ，而功率消耗為28.8mW. 在第二顆晶片中，我提出了一個使用串接式架構的全數位鎖相迴路，輸出的頻率為134百萬赫茲。在這顆晶片中，我利用串接式的架構搭配上注入式鎖像迴路的觀念，藉此消除在單一迴路中，迴路頻寬受限於輸入頻率過低，而產生的相位雜訊過高的問題。實驗的晶片是使用台積電180奈米的互補式金氧半場效電晶體製程。 | zh_TW |
| dc.description.abstract | All-digital phase-locked loop (ADPLL) has recently become more and more popular since it emerges as an attractive alternative to the traditional analog PLL. As comparing with the conventional Charge-pump PLL (CPPLL), the all-digital implemented circuits have the advantage of high portability, small area, high performance in the advanced process, and better integrity in digital system. To develop the potential of ADPLL in more aspects, two chip work base on the ADPLL structure is realized.
In the first work, a 6-GHz All-digital phase-locked loop (ADPLL) based fractional-N frequency synthesizer using embedded FIR filtering technique for delta-sigma modulator (DSM) quantization noise suppression is presented. The basic concept of the algorithm is to use the information from DSM and digitally-controlled oscillator (DCO) period to predict the virtual dividers & phase-frequency detectors (PFDs) output and then compensate the error term in front of the digital-loop filter (DLF). As a result, saves large chip area, as well as power dissipation by the algorithm. The experimental chip is fabricated in a 90 nm 1P9M CMOS process. With the proposed FIR filtering algorithm, the out-of-band DSM quantization noise is suppressed by about 15 dB. The core area is 0.18 mm2 with total power consumption equal to 28.8mW. In the second chip work, a 134-MHz ADPLL using cascaded structure is proposed. The biggest problem in this work is due to the limitation of loop bandwidth (Fref/10), as a results, the DCO noise dominate the total noise flow. To solve the problem, a cascaded PLL structure accompanied with the implementation of sub-harmonic injection-locked PLL in the first stage, hoping to improve the noise performance as comparing with the single stage PLL. The experimental chip is fabricated in a 0.18 um 1P6M CMOS process. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:19:46Z (GMT). No. of bitstreams: 1 ntu-100-R97943112-1.pdf: 1916905 bytes, checksum: af8f1e9cfe4877259562a25be89580df (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES viii LIST OF TABLES xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 Overview of DSM quantization noise reduction technique in fractional-N PLL 3 2.1 Introduction 3 2.2 DAC Cancellation Technique 3 2.2.1 Cancellation by LMS Algorithm [2] 4 2.2.2 Cancellation in All-digital domain [3] 5 2.3 Embedded FIR Filter [5]-[6] 6 2.4 Phase Interpolation[9] 8 2.5 FIR + Phase Interpolation [10] 9 2.6 Summary 11 Chapter 3 A 6GHz FIR Embedded ADPLL Frequency Synthesizer 12 3.1 Introduction 12 3.2 System Architecture and Circuits 13 3.2.1 Phase Frequency Detector 14 3.2.2 9-bit Coarse/Fine combined Vernier TDC 16 3.2.3 Digital Controlled Oscillator 22 3.2.4 Digital Delta-Sigma Modulator 23 3.2.5 Digital Loop Filter 25 3.2.6 Multi-Modulus Divider 27 3.2.7 Delta-Sigma Modulator for MMD 28 3.2.8 Digital FIR filter structure 29 3.3 System Simulation 37 3.4 Experimental Results 39 3.5 Performance Comparison 47 Chapter 4 A 134-MHz All-Digital PLL Using Cascaded Structure 48 4.1 Introduction 48 4.2 Analysis of 2nd order ADPLL 48 4.2.1 Linear Model of the P2D 49 4.2.2 Linear Model of the DLF 51 4.2.3 Linear Model of DCO 52 4.2.4 Design Parameters for Second-Order ADPLLs 53 4.2.5 Design Parameters Calculation 54 4.3 System Architecture and Circuits 56 4.3.1 Phase Frequency Detector and 5-bit TDC 57 4.3.2 Digital Controlled Oscillator [13] 60 4.3.3 Digital Loop Filter 62 4.3.4 Divider 64 4.3.5 Pulse generator & Variable delay chain 65 4.3.6 System analysis & Comparison 66 4.4 System Simulation 69 4.5 Experimental Results 71 Chapter 5 Conclusion 72 Reference 73 LIST OF FIGURES Figure 2.1 Classical quantization noise cancellation technique structure 4 Figure 2.2 DAC gain-calibrated synthesizer using LMS algorithm 5 Figure 2.3 DAC cancellation structure in all-digital domain 6 Figure 2.4 Embedded FIR filter structure for quantization noise reduction 7 Figure 2.5 Traditional FIR filter structure for quantization noise reduction 7 Figure 2.6 Block scheme of the PI – fractional divider 8 Figure 2.7 Detail schematic and timing diagram of the PI – fractional divider 9 Figure 2.8 FIR+PI structure for quantization noise reduction 10 Figure 2.9 Concept of the FIR+PI structure 10 Figure 2.10 Author-proposed blender circuit for FIR filtering 11 Figure 3.1 The proposed 6 GHz ADPLL synthesizer 14 Figure 3.2 The structure of PFD 15 Figure 3.3 The timing diagram of PFD when REF is lead 15 Figure 3.4 The structure of the 6-bit Coarse/Fine Vernier TDC 16 Figure 3.5 The structure of phase selector 17 Figure 3.6 The schematic of a NAND gate 18 Figure 3.7 The schematic of a symmetrical NAND gate 18 Figure 3.8 The structure of the phase decision circuit 19 Figure 3.9 A diagram shows the deadzone of a DFF 19 Figure 3.10 The schematic of the time amplifier 20 Figure 3.11 The simulation result of the time amplifier 20 Figure 3.12 The structure of the 6-bit C/F Vernier TDC 21 Figure 3.13 The simulation result of the 6-bit Fine Vernier TDC 22 Figure 3.14 The structure of the LC-tank DCO 23 Figure 3.15 A first-order DSM (a) block diagram, (b) its digital implementation 24 Figure 3.16 DLF model & bode plot 26 Figure 3.17 Structure of the multi-modulus divider 27 Figure 3.18 Structure of the divide-by-2-or-3 cell 28 Figure 3.19 The block diagram of the second-order MASH 1-1 DSM 28 Figure 3.20 Proposed embedded FIR filter structure 29 Figure 3.21 An example of TDC code & DSM quantization error relation 31 Figure 3.22 The CT_DCO implementation structure 33 Figure 3.23 (a) Transient state of Eq. (3.8) (b) Transient state of Eq. (3.10) 33 Figure 3.24 Behavior simulation for out-of-band phase noise cancellation versus (a) the number of bits of the gain factor gT and (b) the iteration number M. 34 Figure 3.25 Z-domain model of the proposed frequency synthesizer 35 Figure 3.26 Behavior simulation of embedded FIR filter. 38 Figure 3.27 Frequency response of FIR filter technique @ TDC output. 38 Figure 3.28 The die photo 39 Figure 3.29 Integer-N and fractional-N measurement results 41 Figure 3.30 Proposed FIR filter technique measurement 44 Figure 3.31 Measured results of frequency versus cancellation magnitude 44 Figure 3.32 Measured Fractional Spur performance. 45 Figure 3.33 Measured Integer-N PLL locking time w/i lowest loop-bandwidth 45 Figure 3.34 Measured Integer-N PLL locking time w/i biggest loop-bandwidth. 46 Figure 3.35 Measured Integer-N PLL locking time versus bandwidth. 46 Figure 4.1 Block diagram of the all digital phase-locked loop 49 Figure 4.2 Block diagram of the P2D 50 Figure 4.3 Characteristic curve of the P2D 50 Figure 4.4 Linear model of the P2D 51 Figure 4.5 Block diagram of the DLF for a second-order ADPLL 51 Figure 4.6 Linear models of the DLF for a second-order ADPLL 52 Figure 4.7 Linear model of the DCO 53 Figure 4.8 A second-order ADPLL linear model 54 Figure 4.9 The proposed 134MHz cascaded ADPLL structure 57 Figure 4.10 The proposed 134MHz cascaded ADPLL single-stage structure 57 Figure 4.11 The structure of PFD 58 Figure 4.12 The timing diagram of PFD when A is lead 58 Figure 4.13 PFD in series of the 5 bit conventional TDC 59 Figure 4.14 Post simulation result of the TDC resolution and range 59 Figure 4.15 (a) The structure of the DCO (b) The schematic of the delay cell 61 Figure 4.16 Post-simulation of the DCO transfer curve 61 Figure 4.17 A second-order ADPLL s-domain linear model 63 Figure 4.18 Bode plot of the first stage ADPLL with approximated parameters 63 Figure 4.19 Bode plot of the second stage ADPLL with approximated parameters 63 Figure 4.20 First stage divider schematic 64 Figure 4.21 Static logic DFF 65 Figure 4.22 pulse generator & delay chain schematic 65 Figure 4.23 simulation of the single stage structure 67 Figure 4.24 Output phase noise result under S2=N2S1 condition 68 Figure 4.25 simulation comparison of the cascaded structure 68 Figure 4.26 Simulation result 70 LIST OF TABLES Table 3.1 : Target Specifications for 6 GHz ADPLL frequency synthesizer. 13 Table 3.2 : Design Parameters of the ADPLL Synthesizer 25 Table 3.3 : Design Parameters of the ADPLL Synthesizer 37 Table 3.4 : Comparison with Other Works 47 Table 4.1 : Design Parameters of the first stage ADPLL 62 Table 4.2 : Design Parameters of the second stage ADPLL 62 Table 4.3 : Designed value for the largest bandwidth 67 Table 4.4 : Designed value for the largest bandwidth 69 | |
| dc.language.iso | en | |
| dc.title | 一個使用嵌入式有限脈波響應濾波器的60億赫茲除小數頻率合成器 | zh_TW |
| dc.title | A 6 GHz Fractional-N Frequency Synthesizer Using Embedded FIR Filter Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 汪重光(Chorng-Kuang Wang),吳介琮(Jieh-Tsorng Wu),郭泰豪(Tai-Haur Kuo),楊清淵(Ching-Yuan Yang) | |
| dc.subject.keyword | 全數位鎖相迴路,頻率合成器, | zh_TW |
| dc.subject.keyword | ADPLL,FIR,frequency synthesizer, | en |
| dc.relation.page | 74 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2011-08-10 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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