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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃漢邦 | |
dc.contributor.author | Che-Hsin Cheng | en |
dc.contributor.author | 鄭哲欣 | zh_TW |
dc.date.accessioned | 2021-06-08T07:14:25Z | - |
dc.date.copyright | 2008-08-05 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-07-29 | |
dc.identifier.citation | [1] A. Ahmadinia, C. Bobda, S. Fekete, J. Teich and J. Van Der Veen, “Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices,” IEEE Transactions on Computers, Vol. 56, No. 5, pp. 673-680, May 2007.
[2] P. E. Allen, The Practice of Analog IC Design, IEEE Santa Clara Valley Soild-State Circuits Chapter, May 2004. [3] C. W. Chang, “Taiwan Semiconductor Industry: from Foundry to SoC Designs,” SoC Technology Center/ITRI, 2005. [4] W. S. Chang and J. F. Wu, “Full-Custom IC Design Concepts,” National Applied Research Laboratories, National Chip Implementation Center, 2005. [5] T. C. Chen, P. H. Yuh, Y. W. Chang, F. J. Huang and D. Liu, “MP-trees: A Packing-based Macro Placement Algorithm for Mixed-Size Designs,” Design Automation Conference(DAC '07.), San Diego, California, USA, pp. 447-452, June 2007. [6] W. L. Chen, “A Spaceplan Algorithm Using Sequence Triplet Representation,” Master Thesis, Department of Information and Computer Engineering, Chun Yuan Christian University, July 2001. [7] F. T. Cheng, “Introduction to e-Manufacturing,” Chinese Institute of Automation Engineering, pp. 29-40, December 2006. [8] T. K. Chien, “An Empirical Study of Facility Layout Using a Modified SLP Procedure,” Journal of Manufacturing Technology Management, Vol. 15, No. 6, pp. 455-465, 2004. [9] Q. Dong and S. Nakatake, “Constraint-free Analog Placement with Topological Symmetry Structure,” Design Automation Conference (ASPDAC 2008.), Seoul, Korea, USA, pp. 186-191, March 2008. [10] A. Gu and A. Zakhor, “Lossless Compression Algorithms for Hierarchical IC Layout,” IEEE Transactions on Semiconductor Manufacturing, Vol. 21, No. 2, pp. 285-296, May 2008. [11] J. W. Herrmann, “New Directions in Design for Manufacturing,” ASME 2004 Design Engineering Technical Conference and Computers and Information in Engineering Conference, Salt Lake City, Utah, USA, pp. 5-9, September 2004. [12] Y. H. Huang, “The Smart RFID Sensor Design and Localization with RFID Technology,” Master Thesis, Department of Mechanical Engineering, National Taiwan University, July 2007. [13] W. H. Jin, “Development of Automatically Systematic Layout System for Analog IC Layout Design,” Master Thesis, Graduate Institute of Industrial Engineering, National Taiwan University, July 2007. [14] D. A. Johns and K. Martin, Analog Integrated Circuit Design, 1st Edition, New York: John Wiley & Sons, Inc., pp. 394-398, 1997. [15] M. T. Jones, AI Application Programming, 2nd Edition, Massachusetts: Charles River Media, Inc., pp. 229-261, 2005. [16] T. Kerdchuen and W. Ongsakul, “Optimal Measurement Placement for Power System State Estimation Using Hybrid Genetic Algorithm and Simulated Annealing,” International Conference on Power System Technology, Chongqing, China, pp. 1-5, October 2006. [17] K. D. Kim, D. W. Choi, Y. H. Choa and H. T. Kim, “Optimization of Parameters for The Synthesis of Zinc Oxide Nanoparticles by Taguchi Robust Design Method,” Colloids and Surfaces A: Physicochemical Engineering Aspects, Vol. 311, No. 1-3, pp. 170-173, December 2007. [18] P. H. Lin and S. C. Lin, “Analog Placement Based on Hierarchical Module Clustering,” Design Automation Conference (DAC '08.), Anaheim, California, USA, pp. 50-55, June 2007. [19] J. M. Lin, H. E. Yi and Y. W. Chang, “Module Placement with Boundary Constraints Using B*-trees,” IEE Proceedings of Circuits, Devices and Systems, Vol. 149, No. 4, pp. 251-256, August 2002. [20] Y. T. Liu, R. F. Fung and C. C. Wang “Application of the Nonlinear, Double-Dynamic Taguchi Method to the Precision Positioning Device Using Combined Piezo-VCM Actuator,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 54, No. 2, pp. 240-250, February 2007. [21] F. Luo, H. Sun, T. Geng and N. Qi, “Application of Taguchi’s Method in the Optimization of Bridging Efficiency between Confluent and Fresh Microcarriers in Bead-to-Bead Transfer of Vero Cells,” Biotechnology Letters, School of Pharmacy, Shanghai Jiao Tong University, China, Vol. 30, No. 4, pp. 645-649, October 2007. [22] S. E. Martin, “Modifications to the Systematic Layout Planning Procedure to Allow Departmental Division and Irregularly Shaped Sub-Departments,” Master Thesis, Department of Industry Engineering, Ohio University, 2004. [23] M. Mitchell, An Introduction to Genetic Algorithm, First MIT Press Paperback Edition, London: Massachusetts Institute of Technology, pp. 155-179, 1998. [24] D. C. Montgomery, “Experimental Design for Product and Process Design and Development,” Journal of the Royal Statistical Society, Vol. 48, pp. 159-177, 1999. [25] D. C. Montgomery, Design and Analysis of Experiments, 4th Edition, New York: Wiley & Sons Ltd., pp. 363-387, 2002. [26] H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, “Rectangle-Packing-based Module Placement,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, pp. 472-479, November 1995. [27] N. S. Ong and P. K. Li, Genetic Algorithm Approach in PCB Assembly, Integrated Manufacturing Systems, MCB University Press, pp. 256-265, October 1999. [28] H. Onodera, Y. Taniguchi and K. Tamaru, “Branch-and-Bound Placement for Building Block Layout,” ACM/IEEE Design Automation Conference, San Francisco, California, USA, pp. 433-439, June 1991. [29] M. S. Phadke, Quality Engineering Using Robust Design, New York: Prentice- Hall, Inc., pp. 67-94, 1989. [30] D. Rittman, “Design for Manufacturing (DFM),” System Design Frontier, Vol. 2, No. 2, pp. 10-21, November 2005. [31] S. K. Saha, “Managing Technology CAD for Competitive Advantage: An Efficient Approach for Integrated Circuit Fabrication Technology Development,” IEEE Transactions on Engineering Management, Vol. 46, No. 2, pp. 221-229, May 1999. [32] K. Shahookar and P. Mazumder, “A Genetic Approach to Standard Cell Placement Using Meta-Genetic Parameter Optimization,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 5, pp. 500-511, May 1990. [33] C. C. Tsao, “Grey-Taguchi Method to Optimize the Milling Parameters of Aluminum Alloy,” The International Journal of Advanced Manufacturing Technology, Vol. 35, No. 3, pp. 385-393, November 2007. [34] G. M. Wu, Y. C. Chang, and Y. W. Chang, “Rectilinear Block Placement Using B*-Trees,” ACM Transaction on Design Automation of Electronic Systems (TODAES), Vol. 8, No. 2, pp. 188-202, April 2003. [35] F. C. Yang, “Soft Computing,” Course Material, Graduate Institute of Industry Engineering, National Taiwan University, 2007. [36] T. Yang, “Systematic Layout Planning: A Study on Semiconductor Wafer Fabrication Facilities,” International Journal of Operations and Production Management, Vol. 20, No. 11, pp. 1359-1371, November 2000. [37] A. Yodtean and P. Chantngarm, “Hybrid Algorithm for Bisection Circuit Partitioning,” IEEE Region 10 Conference (TENCON 2004), Chiang Mai, Thailand, Vol. 4, pp. 324-327, November 2004. [38] M. Yoshikawa and H. Terai, “A Hierarchical Parallel Placement Technique Based on Genetic Algorithm,” Proceedings of the IEEE International Conference on Intelligent Systems Design and Applications (ISDA’05), Wroclaw, Poland, pp. 302-307, September 2005. [39] M. Yoshikawa and H. Terai, “A Novel Performance-Driven Placement Based on Hybrid Genetic Algorithm,” Proceedings of the IEEE International Conference on Mechatronics & Automation, Niagara Falls, Canada, pp. 1203-1208, July 2005. [40] M. Yoshikawa and H. Terai, “Hybrid Genetic Algorithm Engine for High-Speed Floorplanning,” Proceeding of the European Conference on Circuit Theory and Design, Cork, Ireland, Vol. 1, pp. 189-192, September 2005. [41] L. Zhang, W. F. Huang, C. M. Fang, G. Q. Zhou and S. H. Liu, “Precise Working-Area Layout Planning of Logistics Center,” Conference on Service Systems and Service Management, Changdu, China, pp. 1-6, January 2007. [42] L. Zhang, R. Raut, Y. Jiang, and U. Klein, “Placement Algorithm in Analog-Layout Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 1889-1903, October 2006. [43] L. Zhang, R. Raut, Y. Jiang, U. Kleine and Y. Kim, “A Hybrid Evolutionary Analogue Module Placement Algorithm for Integrated Circuit Designs,” International Journal of Circuit Theory and Applications, Vol. 33, pp. 487-501, May 2005. [44] L. Zhang, C. J. Shi and Y. Jiang, “Symmetry-Aware Placement with Transitive Closure Graphs for Analog Layout Design,” Design Automation Conference (ASPDAC 2008.), Seoul, Korea, pp. 180-185, March 2008. [45] 曹祖聖,Visual C#.net程式設計經典,初版六刷,台灣台北,文魁資訊股份有限公司,2006年3月。 [46] 黃聰明,C#物件導向程式設計,出版二刷,台灣台北,文魁資訊股份有限公司,2003年9月。 [47] http://en.wikipedia.org/wiki/Capacitor [48] http://en.wikipedia.org/wiki/Genetic_algorithm [49] http://en.wikipedia.org/wiki/Inverter_(electrical) [50] http://en.wikipedia.org/wiki/Manhattan_distance [51] http://en.wikipedia.org/wiki/NAND [52] http://en.wikipedia.org/wiki/Resistor [53] http://en.wikipedia.org/wiki/Switch [54] http://en.wikipedia.org/wiki/Transistor [55] http://smtbook.com/instructor_guide.pdf [56] http://www.kopin.com/cyberdisplay/world-class-manufacturing/ [57] http://www.tekpool.com/?p=23 [58] http://www.ti.com/corp/docs/press/company/2003/c03137.shtml | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26542 | - |
dc.description.abstract | 隨著半導體產業的蓬勃發展,為了提升競爭力與增加收益,半導體產品的開發時程也日益緊縮。本研究旨在針對類比式電路產品開發流程中的佈局設計部分提出改善方法,期能縮短類比式電路產品開發時程。
對類比式電路產品而言,佈局設計對產品的最終成效影響甚大,佈局設計也是一項高度依賴設計人員的經驗與專業技巧之工作。為了提升類比式電路產品開發的整體效率,本研究提出一個類比式IC設計之自動化佈局系統,此系統以考量晶片面積利用率、電路元件之關連關係與電路元件的熱能消耗此三要素,透過系統佈置設計(SLP)流程與基因演算法之求解,以改良式樹狀結構的佈局方式,在短時間內快速提供設計人員最適合的佈局方式。 本研究最後以類比式電路產品為例,透過此自動化佈局系統重新進行佈局設計,並透過模擬與實際上的比較來驗證此系統。 | zh_TW |
dc.description.abstract | Due to the continuous breakthrough of manufacturing process and market expansions in semiconductor industry, semiconductor product development time is more and more tighten for reducing time to market, and increasing the benefits of the upstream and downstream members in the design chain. The focus of this research is the development of automatic layout system which is expected to improve the layout design procedure for analog IC product developments.
Obviously, layout extremely affects the performance of analog IC products, and it is truly a time-consuming work to develop an analog IC products. Moreover, the layout design procedure of analog IC highly depends on designer’s experience and expertise. In order to improve the efficiency of analog IC product development process, automatic layout system (ALS) is established in this research for providing layout design pattern quickly. Core chip area utility ratio, input/output relationship between components and the power consumption produced from thermal noise of analog circuits are concerned in automatic layout system, and layout patterns through a revised tree-structure methodology can be acquired quickly. The layout problem is solved through systematic layout planning (SLP) process flow and genetic algorithm (GA). Designers can acquire the suitable layout pattern immediately from automatic layout system. To verify this automatic layout system, two existing analog IC products are chosen as testing samples. The comparisons between actual layout and layout from automatic layout system are listed in the following content. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:14:25Z (GMT). No. of bitstreams: 1 ntu-97-R95546010-1.pdf: 7427845 bytes, checksum: 9f952d1160fa21805badcf3dea5a6f45 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | List of Tables vi
List of Figures vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contributions 2 1.3 Thesis Organization 4 Chapter 2 Relevant Research and Background Knowledge 5 2.1 Semiconductor Manufacturing Process 5 2.2 Analog IC Product Development Process 9 2.2.1 Introduction to Analog IC Design 9 2.2.2 Mask, Manufacturing, Packaging, and Testing 16 2.3 Systematic Layout Planning 19 2.4 Genetic Algorithm 22 2.5 Taguchi Method 29 Chapter 3 Consideration of Analog IC Layout Design 33 3.1 Differences between Digital and Analog IC 33 3.2 Solve the Layout Problem through SLP Methodology 34 3.3 Layout Performance Indices 37 3.3.1 Chip Area 38 3.3.2 IO-relationship 39 3.3.3 Power Consumption 41 Chapter 4 Automatic Layout System 44 4.1 Data Input 44 4.1.1 Capacitor 45 4.1.2 Resistor 49 4.1.3 Transistor 51 4.1.4 Inverter 56 4.1.5 NAND Gate 57 4.1.6 Switch 59 4.1.7 Arrangement Units 60 4.2 Automatic Layout Algorithm 63 4.2.1 Revised Tree-Structure Methodology 63 4.2.2 Non-Overlapping Check 66 4.3 GA Algorithm 69 4.3.1 Computing Flow 70 4.3.2 Chromosomes Encoding 71 4.3.3 Fitness Function 72 4.3.4 GA Operations 73 4.3.5 Termination 78 4.4 Parameter Optimization 78 4.4.1 Factor Selection 79 4.4.2 Experimental Results 80 Chapter 5 Application and Case Study 83 5.1 RF to DC 83 5.1.1 Requirement of Basic Components 84 5.1.2 Arrangement Units and Layout Results 85 5.1.3 Implementation and Comparison 90 5.2 DC-BIAS 95 5.2.1 Requirement of Basic Components 95 5.2.2 Arrangement Units and Layout Results 99 5.2.3 Implementation and Comparison 103 Chapter 6 Conclusions and Future Works 110 6.1 Conclusions 110 6.2 Future Works 111 References 113 | |
dc.language.iso | en | |
dc.title | 以基因演算法為基礎之類比IC設計自動化佈局系統 | zh_TW |
dc.title | A GA-based Automatic Layout System for Analog IC Layout Design | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭瑞祥,張耀文,陳文耀 | |
dc.subject.keyword | 類比電路,佈局系統,面積利用率,元件關連關係,熱能消耗,基因演算法, | zh_TW |
dc.subject.keyword | Analog IC,Automatic Layout System,Chip Area Utility Ratio,Input/Output Relationship,Power Consumption,Genetic Algorithm, | en |
dc.relation.page | 118 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-07-30 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 工業工程學研究所 | zh_TW |
顯示於系所單位: | 工業工程學研究所 |
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