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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26503完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 盧奕璋(Yi-Chang Lu) | |
| dc.contributor.author | Chun-Yen Lin | en |
| dc.contributor.author | 林俊彥 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:12:47Z | - |
| dc.date.copyright | 2008-08-06 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-31 | |
| dc.identifier.citation | [1] R. S. Patti “Three-dimensional integrated circuit and the future of system-on-chip design” Proc. Of IEEE, vol. 94, No. 6, June 2006.
[2] K. Banerjee, et al. “3D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration” Proc. of IEEE, Vol.89, No.5, May 2001. [3] M. Koyanagi et al. “Design of 4-kbit×4-Layer optically coupled three-dimensional common memory for parallel processor system” IEEE J. Solid-State Circuits, Vol. 25, No. 1, Feb. 1990 [4] M. Dreiza, et al. “High density PoP(package on package) and package stacking development” Electronic Components and Technology Conference, Proc. 57th May 29 2007-June 1 2007 pp.1397 - 1402 [5] T. Fukushima, et al “New three-dimensional integration technology using self-assembly technique” IEEE International Electron Device Meeting Technical Digest, pp 348-351, Dec 2005. [6] M. Koyanagi, et al. “Three-dimensional integration technology based on wafer bonding with vertical buried interconnections” IEEE Trans. Electron Devices, Vol.53, No.11, Nov 2006. [7] J. A. Burns, et al “A wafer-scale 3-D circuit integration technology” IEEE Trans. Electron Devices, Vol.53, No.10, Oct 2006. [8] K. Bernstein, et al “Interconnects in third dimension: design challenges for 3D ICs” DAC '07. 44th ACM/IEEE, June 2007 pp.562 - 567 [9] J. U. Knickerbocker, et al “3-D silicon integration and silicon packaging technology using silicon through-vias” IEEE J. Solid-State Circuit, Vol. 41, No. 8, Aug 2006. [10] S. Pozder, et al “Progress of 3D integration technologies and 3D interconnects” IEEE Int. Interconnect Technol. Conf., June 2007 pp.213 - 215 [11] C. ferri, et al.“Strategies for improving the parametric yield and profits of 3D ICs” IEEE/ACM In. Conf. Nov. 2007 pp.220 - 226 [12] S. M. Jung, et al “Highly cost effective and high performance 65nm S3 (stacked single-crystal Si) SRAM technology with 25F2, 0.16μm2 cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications” Symp. VLSI Technology Dig. of Technical Papers, pp.220-221, June, 2005. [13] J. E. Leland and R. Ponnappan “Experimental investigation of an air microjet array impingement cooling device” J. Thermophysics and Heat Transfer, Vol. 16, No.2, April-June 2002. [14] A. Pal, et al. “Design and performance evaluation of a compact thermosyphon” IEEE Trans. Compon. Packag. Technol., Vol. 25, No.4, Dec 2002. [15] L. Jiang, et al. “Closed-loop electroosmotic microchannel cooling system for VLSI circuits” IEEE Trans. Compon. Packag. Technol., Vol. 25, No. 3, Sep 2002. [16] J. Cong and Y. Zhang “Thermal via planning for 3-D ICs” IEEE Int. Conf. Comput.-Aided des., pp745-752, Nov 2005. [17] Koo et al. “Integrated microchannel cooling for three-dimensional electronic circuit architectures.”ASME J. of Heat Transfer, Vol. 127, pp. 49-58, Jan 2005. [18] P. D. Franzon, et al. “Design for 3D integration and applications” IEEE, Int. Symp. Signal, Systems and Electronics, pp.263-266, 2007. [19] W. Wang, et al. “Nonvolatile SRAM cell” IEEE Int. Electron Devies Meeting Technical Dig., Dec 2006. [20] K. Zoschke, et al. “Fabrication of application specific integrated passive devices using wafer level packaging technologies” IEEE Trans. Adv. Packag., Vol. 30, No. 3, Aug, 2007. [21] E. Seevinck, et al. “Static-noise margin analysis of MOS SRAM cells” IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, OCT 1987. [22] K. Takeda, et al, “A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications” IEEE J. Solid-State Circuit, Vol. 41, No. 1, JAN 2006. [23] N. Verma and A. P. Chandrakasan “A 65nm 8T sub-V SRAM employing sense-amplifier redundancy” IEEE Int. Solid-State Ciucuits, pp.328-330, Jun. 2007 [24] Kiyoo Itoh “VLSI Memory Chip Design” Springer 2001 [25] B. D. Yang and L. S. Kim “ A low-power SRAM using hierarchical bit line and local sense amplifiers” IEEE J. Solid-State Circuits, vol.40, no.6, June 2005. [26] A. W. Topol, et al, “Three-dimensional integrated circuit” IBM J. RES. & Dev. Vol. 50 No. 4/5 July/Sep. 2006 [27] P.D. Franzon, et al, “Design for 3D integration and application” Int. Symp. Signals, System and Electronics, pp.263-266, 2007. [28] I. Kiyoo, et al. “Trends in low-power RAM circuit technologies” Proc. IEEE, vol.83, pp.524-543, April 1995. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26503 | - |
| dc.description.abstract | 本文以直通矽晶穿孔(TSV)、靜態隨機存取記憶體、以及製程漂移三個部份進行研究。第一個部份主要著重於三維電路垂直連接訊號之穿孔，就其架構、尺寸、可能之漂移以及與導線連接之堆疊架構以電磁模擬軟體來進行剖析。第二個部份進行隨機存取記憶體之電路介紹和操作原理，並分析其記憶體單元之靜態雜訊容限以及放電能力。第三個部份則涵括前一、二部份進來，將TSV製作時可能發生的製程漂移進行電性的粹取，以及將靜態隨機存取記憶體之記憶體單元做Monte Carlo的模擬以得到SNM-Icell的分布圖，藉以了解製程漂移對穿孔或記憶體單元的影響。最後結合記憶體電路與粹取的3D導線模型來模仿雙層堆疊的記憶體，並以製程漂移模擬軟體驗證其資料的輸出正確性，能夠比較2D/3D的電路表現以及對於製程漂移的抵禦能力。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:12:47Z (GMT). No. of bitstreams: 1 ntu-97-J95921024-1.pdf: 8122272 bytes, checksum: 5b39e8140b440bdaf4a7d18e8f284621 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 第一章 簡介(1)
1.1 動機(1) 1.2 研究架構(2) 第二章 3D電路技術(4) 2.1 簡介(4) 2.2 封裝堆疊(Package Stacking)(6) 2.3 晶片堆疊(Die Stacking)(7) 2.4 晶圓堆疊(Wafer Stacking)(9) 2.5 元件堆疊(Device Stacking)(11) 2.6 新興3D電路技術(14) 第三章 直通矽晶穿孔(TSV)(18) 3.1 簡介(18) 3.2 單一直通矽晶穿孔(20) 3.3 直通矽晶穿孔耦合效應(24) 3.4 直通矽晶穿孔及繞線之阻抗粹取(25) 第四章 靜態隨機存取記憶體(SRAM)電路架構及操作分析(30) 4.1 靜態隨機存取記憶體單元模擬(30) 4.1-1 靜態噪聲容限(SNM)(30) 4.1-2 放電電流(I-cell)(32) 4.2 靜態隨機存取記憶體架構(33) 4.3 靜態隨機存取記憶體之讀、寫操作時序(38) 4.4 時域及功率分析(40) 4.5 特殊電路架構及應用(44) 第五章 3D SRAM 電路模擬(46) 5.1 設計餘量(Design Margin)(46) 5.2 Monte Carlo下之SNM-Icell(47) 5.3 隨機存取記憶體設計(52) 5.4 模擬結果(54) 5.5 2D溫度/電壓/製程漂移模擬(56) 5.6 3D溫度/電壓/製程漂移模擬(59) 5.7 2D/3D模擬結果(60) 第六章 結論(65) 參考文獻(67) | |
| dc.language.iso | zh-TW | |
| dc.subject | 靜態隨機存取記憶體 | zh_TW |
| dc.subject | 三維電路 | zh_TW |
| dc.subject | 直通矽晶穿孔 | zh_TW |
| dc.subject | 堆疊 | zh_TW |
| dc.subject | SRAM | en |
| dc.subject | Chip Stacking | en |
| dc.subject | 3D Circuit | en |
| dc.subject | TSV | en |
| dc.title | 直通矽晶穿孔與靜態隨機存取記憶體 | zh_TW |
| dc.title | Through Silicon Via and Static Random Access Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧信嘉,陳信樹,郭宇軒 | |
| dc.subject.keyword | 三維電路,直通矽晶穿孔,堆疊,靜態隨機存取記憶體, | zh_TW |
| dc.subject.keyword | 3D Circuit,TSV,SRAM,Chip Stacking, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-97-1.pdf 未授權公開取用 | 7.93 MB | Adobe PDF |
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