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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26405完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳德玉(Dan Chen),劉志文(Chih-Wen Liu) | |
| dc.contributor.author | Chung-Shu Lee (Martin Lee) | en |
| dc.contributor.author | 李忠樹 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:09:05Z | - |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-01 | |
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Zhou, P-L Wong, K. Yao, and F. C. Lee, “Design and performance evaluation of multi-channel interleaving quasi-square-wave buck voltage regulator module,” Proc. HFPC, 2000, pp. 82-88. [9] X. Zhou, “Low-voltage high-frequency fast-transient voltage regulator module,” Ph.D. Dissertation, Virginia Tech, Blacksburg, VA, July 1999. [10] X. Zhou, P.-L Wong, R. Watson, L. Amoroso, X. Sun, H. Wu, P. Xu, B. Yang, W. Chen, M. Donati, F.C. Lee and A. Q. Huang, “Voltage regulator module for future generation processors,” VPEC Annual Seminar Tutorial, 1998. [11] X. Zhou, X. Zhang, J. Liu, P.-L Wong, J. Chen, H. Wu, L. Amoroso, F.C. Lee and D. Chen, “Investigation of candidate VRM topologies for future microprocessors,” Proc. IEEE APEC, 1998, pp. 145-150. [12] G. Capponi, L. Minneci, F. Librizzi and P. Scalia, “Multiphase voltage regulator module with transient step changing phase,” Proc. IEEE PowerCon, 2000, pp. 463-467. [13] P. Xu, X. Zhou, P. Wong, K. Yao and F. C. Lee, “Interleaved VRM cuts ripple, improves transient response,” Proc. PCIM Power Electronic System, Feb. 2001, pp. 70-78. [14] Yuancheng Ren, Kaiwei Yao, Ming Xu and Lee, F. C., “Analysis of the power delivery path from the 12-V VR to the microprocessor,” IEEE Trans. on Power Electronics, vol. 19, Nov. 2004, pp. 1507-1514. [15] J. A. A. Qahouq, O. Abdel-Rahman, L. Huang, I. Batarseh, “On load adaptive control of voltage regulators for power managed loads: control schemes to improve converter efficiency and performance,” IEEE Trans. on Power Electronics, Sept. 2007, pp. 1806-1819. [16] Waizman, A. and Chee-Yee Chung, “Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology,” IEEE Trans. on Advanced Packaging, vol. 24, Aug. 2001, pp. 236-244. [17] Kaiwei Yao, Yuancheng Ren and Lee, F.C., “Critical bandwidth for the load transient response of voltage regulator modules,” IEEE Trans. on Power Electronics, vol. 19, Nov. 2004, pp. 1454-1461. [18] K. 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[24] Intel Document, “VRM 9.0 DC-DC conveter design guidelines,” Apr. 2001. [25] Peterchev, A.V. and Sanders S.R., “Load-line regulation with estimated load-current feedforward: application to microprocessor voltage regulators,” IEEE Trans. on Power Electroics, vol. 21, Nov. 2006, pp. 1704-1717. [26] P. L. Wong, “Performance improvements of multi-channel interleaving voltage regulator modules with integrated coupling inductors,” Ph.D. Dissertation, Virginia Tech., Blacksburg, VA, March 2001. [27] R. Miftakhutdinov, “Optimal design of interleaved synchronous buck converter at high slew-rate load current transients,” Proc. IEEE PESC, 2001, pp. 1714-1718. [28] A. R. Brown and R. D. Middlebrook, “Sampled-data modeling of switching regulators,” Proc. IEEE PESC, 1981, pp. 349-369. [29] Yang Qiu, Ming Xu, Kaiwei Yao, Juanjuan Sun and F. C. Lee, “The multi-frequency small-signal model for buck and multiphase interleaving buck converters,” Proc. IEEE APEC, 2005, pp. 392-398. [30] R. Redl, B.P. Erisman and Z. Zansky, “Optimizing the load transient response of the buck converter,” Proc. IEEE APEC, 1998, pp. 170-176. [31] G.K. Schoneman and Mitchell, “Output impedance considerations for switching regulators with current-injection control,” Proc. IEEE PESC, 1987, pp. 324-335. [32] L. D. Varga and N.A. Losic, “Synthesis of zero-impedance converter,” IEEE Trans. on Power Electronics, vol. 7, Jan. 1997, pp. 152-170. [33] R. Redl, B. P. Erisman, “Designing minimum cost VRM8.2/8.3 compliant converters,” Proc. HFPC, 1998, pp. 172-181. [34] B. C. Kuo and F. Golnaraghi, Automatic Control Systems, John Wiley & Sons, Inc. 2003. [35] R. B. Ridley, B. H. Cho and F. C. Lee, “Analysis and interpretation of loop gains of multiloop-controlled switching regulators,” IEEE Trans. on Power Electronics, vol. 3, Oct. 1988, pp. 489-498. [36] Intersil document, “Microprocessor core voltage regulator two-phase buck PWM controller ISL6560 datasheet”. [37] C-J. Chen, D. Chen, M. Lee and E. Tseng, “Design and modeling of a novel high-gain peak current control scheme to achieve adaptive voltage positioning for DC Power Converters,” Proc. IEEE PESC, 2008, June 2008. [38] Xiaoming Duan, Jinseok Park, Alex Q. Huang, “A novel current mode variable frequency control for dc-dc converters with adaptive voltage positioning,” Proc. IEEE PESC, 2006, June 2006, pp. 1607-1611. [39] S. Chikamenahalli, K. Aygun, M. J. Hill, K. Radhakrishnan, K. Eliert, E. Standord, “Microprocessor platform impedance characterization using VTT tools,” Proc. IEEE APEC, 2005, pp. 1466-1469. [40] B. Wang, S. Wang, D. Chen, K. Huang, B. Tai and E. Tseng, “Practical simulation of control characteristics of a current-mode dc/dc converter,” Proc. IEEE PESC, 2006. pp. 569-573. [41] B. Choi, “Step load response of a current-mode-controlled dc-to-dc converter,” IEEE Trans. Aerospace and Electronic System, vol. 33, no. 4, Oct. 1997. [42] Rictek document, “4/3/2/1-Phase PWM Controller RT8805 datasheet”. [43] US Patent No. 5,747,976, 'Constant on-time architecture for switching regulators,' 1998. [44] J. Abu-Qahouq, Mao Hong, I. Batarseh, “Multiphase voltage-mode hysteretic controlled dc-dc converter with novel current sharing,” IEEE Trans. on Power Electronics, vol. 19, Nov. 2004, pp. 1397-1407. [45] Jian Sun, “Small-signal modeling of variable-frequency pulse-width modulators,” IEEE Trans. Aerospace and Electronic System, vol. 38, July 2002, pp. 1104-1108. [46] C. M. de Oliveiria Stein, J. R. Pinherio and H. L. Hey, “A ZCT auxiliary communication circuit for interleaving boost converters operating in critical conduction mode,” IEEE Trans. on Power Electronics, vol. 17, Nov. 2002, pp. 954-962. [47] P. Alou, J.A. Cobos, R. Prieto, O. Garcia and J. Uceda, “A two stage voltage regulator module with fast transient response capability,” Proc. IEEE PESC, 2003, pp. 138-143. [48] T. Nabeshima, T. Sato, S. Yoshida, S. Chiba, K. Onda, “Analysis and design considerations of a buck converter with a hysteretic PWM controller,” Proc. IEEE PESC, 2004, pp. 1711-1716. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26405 | - |
| dc.description.abstract | 適應性電壓位置(Adaptive voltage position, AVP)控制已被應用在微處理器電源供應器中的多相式電壓調整器，適應性電壓位置可以提高電源轉換器的效率同時降低輸出電容的使用量。本論文主要便是探討適應性電壓位置的控制電路分析。
適應性電壓位置控制與一般電源電路使用的非適應性電壓位置控制最大的不同在於控制迴路的設計法則，由於控制迴路會影響閉迴路之輸出阻抗，所以具適應性電壓位置控制的控制器必須設計控制迴路來達到所謂固定輸出阻抗的需求。控制迴路除了影響閉迴路之輸出阻抗之外，也會影響其他閉迴路之特性如輸入電壓調整率及控制穩定度，因此，必須利用較準確的數學模型來設計所需之固定輸出阻抗並同時滿足其他特性。 本論文中將會分析名為AVP+的新型適應性電壓位置設計。為了深入探討控制迴路性能，例如控制迴路穩定度、輸出阻抗以及輸入電壓調整率，AVP+控制的電壓調整器的小訊號模型已被推導出來，且經由實驗和模擬已證明了此項模型可做為小訊號分析基礎。這是先前從未被研究探討的。 本文將以AVP+ 控制與另一個常用的適應性電壓位置控制(在此稱作AVP- control)及電流模式控制(Current-mode control)作比較，對於目前輸出電容朝小型化的發展，使用陶瓷電容和高頻切換已成為現在的主流趨勢。本文也針對此種條件做分析比較。經由分析及模擬能證明AVP+控制相對於AVP-控制是能得到較佳的穩定度及輸出阻抗特性，所以AVP+控制是比較符合電壓調整器的未來特性需求。 | zh_TW |
| dc.description.abstract | Adaptive voltage positioning (AVP) technique has been used in multiphase voltage regulators for microprocessor power applications. It is a control scheme to increase the energy efficiency and reduce the output capacitor size of a DC power converter. The focus of the dissertation is on the control aspect of the AVP schemes.
The design philosophy of AVP control is very different from that of a conventional DC power converter. In such a design, the converter output impedance must be designed to be a prescribed constant value with respect to frequency. As a result, the control loop gain must be shaped in certain way to accomplish AVP. Besides the issue of output impedance, the issues of line regulation and control stability must also be considered at the same time. Without a detailed mathematical model, this is very hard to achieve. In this dissertation, a novel scheme introduced in recent years, called AVP+, was for the first time analyzed. Small signal model was developed from which compensator design can be accomplished. The model has been verified by simulations and experiments. Comparisons were made of this scheme with two well-known conventional schemes, the current-mode scheme and the AVP- scheme. Compared to conventional AVP schemes, the AVP+ scheme provides better stability margin, better output impedance performance while maintaining good line regulation. This is especially true for the case of using ceramic output capacitors and high switching frequency, which is the prevailing trend of high-performance voltage regulators. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:09:05Z (GMT). No. of bitstreams: 1 ntu-97-D92921006-1.pdf: 3522452 bytes, checksum: 5e49e0e23a198b3044e0e5a8452c061d (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1. Background: Voltage Regulators 1 1.2. Trend of Voltage Regulators Technology 3 1.3. Focus and Contributions of this Dissertation 8 1.4. Dissertation Outline 9 Chapter 2 Concept of Constant Output Impedance 11 2.1. Introduction 11 2.2. Constant Output Impedance 12 2.3. Transfer Functions of the Small-Signal Model 17 Chapter 3 AVP+ Control Scheme 25 3.1. Circuit Development for AVP+ Control Scheme 25 3.1.1. Compensator with Infinite Gain Design 27 3.1.2. Compensator with Finite Gain Design 28 3.1.3. Compensator for AVP+ Control Scheme 32 3.2. Control Loop Model of AVP+ Control Scheme 34 3.3. Design for a Constant Output Impedance with AVP+ 39 3.4. Experimental Results 43 3.5. Summary 47 Chapter 4 Comparisons of Various AVP Schemes 48 4.1. Comparisons of the Three Schemes 48 4.1.1. Control Block Diagrams and Transfer functions 48 4.1.2. Design for constant output impedance for AVP 53 4.1.3. Comparisons in simulations and analytical mdoel 57 4.2. Peaking Effect of AVP+ and AVP- 67 4.2.1. Peaking Effect of T2 and Zoc 70 4.2.2. Simulation Results 73 4.3. Summary 75 Chapter 5 Conclusions 76 5.1. Summary 76 5.2. Suggested Future Works 78 References 79 Vita 84 | |
| dc.subject | 主動式電壓降控制 | zh_TW |
| dc.subject | AVP+控制 | zh_TW |
| dc.subject | 電壓調整器 | zh_TW |
| dc.subject | 穩定度 | zh_TW |
| dc.subject | 固定輸出阻抗 | zh_TW |
| dc.subject | 輸入音頻擾動衰減率 | zh_TW |
| dc.subject | stability | en |
| dc.subject | active droop control | en |
| dc.subject | audio susceptibility | en |
| dc.subject | AVP+ control | en |
| dc.subject | voltage regulator | en |
| dc.subject | constant output impedance | en |
| dc.title | 具適應性電壓位置控制之電壓調整器之分析與設計 | zh_TW |
| dc.title | Analysis and Design of Voltage Regulators with Adaptive Voltage Position (AVP) Control | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 許源浴,劉昌煥,劉添華,羅有綱,潘晴財,廖聰明,陳建富 | |
| dc.subject.keyword | AVP+控制,電壓調整器,穩定度,固定輸出阻抗,輸入音頻擾動衰減率,主動式電壓降控制, | zh_TW |
| dc.subject.keyword | AVP+ control,voltage regulator,stability,constant output impedance,audio susceptibility,active droop control, | en |
| dc.relation.page | 84 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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