以Verilog轉換SystemC完成多核心嵌入式處理器之效能模型

Abstract

近年來，因為消費性店商品生命週期大幅縮短，為了更快速地開發出新產品，軟硬體共同設計（hardware/software co-design）的重要性越來越受到重視。使用傳統Verilog或是VHDL開發硬體，要和系統層級整合時，介面往往不易操作，有很多的限制，而且相當依賴工具的能力。SystemC，除了可以描述硬體的細節，也可以很方便的和軟體整合，系統介面的設計也具有相當的彈性，能適應軟硬體共同設計的複雜度。為了讓傳統大量Verilog撰寫的矽智財可以轉移到SystemC的開發環境，Verilog轉換SystemC的研究成為一個重要的議題。 在本論文中，我們介紹一套Verilog-to-SystemC的轉譯工具，稱為V2X。針對傳統轉譯工具制式化的設計哲學，V2X採取新的設計概念。傳統的轉換工具為了完成特定的轉換結果，犧牲一些Verilog語法的支援，致使無法產生正確的轉譯結果。為了克服這樣的問題，我們的V2X工具採用兩階段轉換的架構，區分為Verilog語意的萃取和後續彈性轉換兩個部分。本文最後，我們將使用OpenSPARC T1做為案例討論，轉譯出一個和原本Verilog版本相符的SystemC OpenSPARC T1。我們轉換過的SystemC模型相較原本Verilog的模型，進行模擬時，獲得效能上相當的改善。

With the life-cycle of consumer electronics getting short in recent years, to shorten development time, hardware/software co-design has become an important issue. Traditionally, hardware description languages, e.g. Verilog and VHDL, are commonly used to describe and model the hardware. Unfortunately, the usage of language is hard to be integrated with the development of software. SystemC solves this problem by describing the hardware with C++ language and C++ language library functions. However, converting an existing Verilog design can be very challenging. Existing tools failed to produce correct translation for sophisticated Verilog code, such as OpenSPARC T1. They cannot support certain Verilog constructs because it is hard to translate these constructs directly into SystemC to maintain correct semantics. Thus, we designed an innovative Verilog-to-SystemC translation tool, called V2X, with techniques developed to overcome those problems. We took a two-stage approach to make the translation flexible and extendible. In this thesis, we describe how performance modeling can be done for multicore embedded processors based on Verilog-to-SystemC conversion, with OpenSPARC T1 as a case study. Using V2X, we successfully translated OpenSPARC T1 design into SystemC, and we show that the SystemC version improved the simulation speed by ~40 times.