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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 曹恆偉 | |
dc.contributor.author | "Chia-Tseng ,Chiang" | en |
dc.contributor.author | 江家增 | zh_TW |
dc.date.accessioned | 2021-06-08T06:58:09Z | - |
dc.date.copyright | 2009-07-21 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-09 | |
dc.identifier.citation | [1] Serial ATA Workgroup “SATA: High speed Serialized AT Attachment, ”Revision 1.0,26 May 2004
[2] V. H. Kee, “EMI Compliance by Design,” http://www.ultratech-labs.com, Oct. 2001. [3] http://www.serialata.org [4] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 227-231, 1994. [5] EDN Design Feature “Use spread-spectrum techniques to reduce EMI”. [6] “Spread Spectrum Timing for Hard Disk Drive Applications,” http://www.cypress.com, Nov. 2000. [7] “Intel Pentium 4 Processor in the 423-pin package EMI Guideline,” http://www.intel.com, Oct. 2000. [8] http://www.fulcrum.ru/Documents/CDROMs/NS/htm/nsc00596.htm [9] S. Bolger and S. O. Darwish, “Use spread-spectrum techniques to reduce EMI,”EDN; Boston, Vol.43, May 21, 1998. [10] F.Lin and D.Y.Chen, “Reduction of Power Supply EMI Emission by Switching Frequency Modulation,” in Proc. IEEE Power Electron. Spec. Conf., pp. 127-133, 1993. [11] S. Haykin, “Communication Systems.” 3rd ed. New York: Wiley, 1994. [12] M. T. Zhang, “Notes on SSC and Its Timing Impacts,” http://www.intel.com, Feb. 1998. [13] H. S. Black. “Modulation Theory”, New York: Van Nostrand, 1953. [14] K. B. Hardin, J. T. Fessler, A. L. Cable, and M. L. Pulley, “Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility,” in Proc. IEEE Int. Symp.Electromagnetic Compatibility, pp. 302-307, 1997. [15] H. H. Chang, I. H. Hua, S. I. Liu, “A Spread-Spectrum Clock Generator With Triangular Modulation,” IEEE J. Solid-State Circuits, vol.38, no.4, pp. 673-676, Apr. 2003. [16] H. R. Lee, O. Kim, G. Ahn, D. K. Jeong, “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-channel SATA Tranceiver in 0.18um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers., pp. 162-163, Feb. 2005. [17] Aoyama, M.; Ogasawara, K.; Sugawara, M.; Ishibashi, T.; Shimoyama, S. et al. '3 Gbps 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA,' in Symp. VLSI Circuits Dig. Tech. Papers, pp. 107-110, Jun. 2003. [18] W. T. Chen, J. C. Hsu, H. W. Lune, C. C. Su, “A Spread Spectrum Clock Generator for SATA-Ⅱ,?in Proc. IEEE Int. Symp. Circuits and Systems, pp. 2643-2646, 2005. [19] Kokubo, M.; Kawamoto, T.; Oshima, et al., 'Spread-spectrum clock generator for serial ATA using fractional PLL controlled by Delta Sigma modulator with level shifter,' in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers. pp.160-161, Feb. 2005. [20] I.T. Sha 'Spread spectrum at phase lock loop (PLL) feedback path' U.S Pat. No 6,377,646, Apr. 2002. [21] L. William, V. H. Chu 'Apparatus and method for spread spectrum clock generator with accumulator' U.S Pat. No 7,443,905, Oct. 2008. [22] N. Chawla 'Spread spectrum clock generator' U.S Pat. No 2008/0129351 Al, Jun. 2008. [23] C. Kim et al. 'Apparatus and method for clock generator with pecewise linear modulation' U.S Pat. No 2009/0083567 A1, Mar. 2009. [24] K. D. Chen 'Asymmetry triangular frequency modulation profiles for spread spectrum clock generator' U.S Pat. No 7,508,278, Mar. 2008. [25] Roland E. Best, Phase-Locked Loops Theory Design, Simulation, and Applications, McGraw-Hill international editions, 1993 [26] B. De Muer and M.S.J. Steyaert, “A CMOS Monolithic ΔΣ-Controlled Fractional-N Frequency Synthesizer for DCS-1800,” IEEE J. Solid-State Circuits, vol. 37, no. 7, Jul. 2002, pp. 835-844. [27] W. Rhee, B.S. Song, and A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a Third-Order ΔΣ Modulator,” IEEE J. Solid-State Circuits, vol. 35, no. 10, Oct. 2000, pp. 1453-1460,. [28] B. Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998. [29] T.A.D. Riley, M.A. Copeland, and T.A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, May 1993,pp. 553-559,. [30] B. Miller and B. Conley, “A Multiple Modulator Fractional Divider,” in Proc. IEEE Frequency Control Symp. Mar. 1990, pp. 559-568. [31] Roland E. Best, Phase-Locked Loops Theory Design, Simulation, and Applications, McGraw-Hill international editions, 1993 [32] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” in National Semiconductor Appl. note. 1001, May 1996. [33] S.Sedra and K.C.Smith ,“Microelectronic Circuits”, Oxford University Press: Fourth Edition, 1997. [34] J. G. Maneatis, “Low jitter Process-Independent DLL and PLL Based on Self-biased Techniques,” IEEE J. Solid-State Circuits, vo.l31, no.11, pp.1723-1732, Nov. 1996. [35] Chan-Hong Park; Beomsup Kim, 'A low-noise, 900-MHz VCO in 0.6-μm CMOS' IEEE J. Solid-State Circuits, vol.34, no.5, pp. 586-591, May 1999. [36] D. Theil and C. Durdodt, “A Fully Integrated CMOS Frequency Synthesizer for Bluetooth,” in Proc. RFIC, Phoenix, AZ, pp. 103-106, 2001. [37] C. S. Vaucher et al, “A family of low-power truly modular programmable divider in standard 0.35um CMOS technology” IEEE J. Solid-State Circuits vol. 35, no.7, pp. 1039-1045, July 2000. [38] M. Kozak and I. Kale, “A pipelined noise shaping coder for fractional-N frequency synthesizer” IEEE trans.on Instrumentation and Measurement, vol. 50, pp. 1154-1161, Oct. 2001. [39] Myung-Woon Hwang; Jong-Tae Hwang; Gyu-Hyeong Cho, 'Design of high speed CMOS prescaler,' in Proc. Second IEEE Asia- Pacific Conference on Advanced System Integrated Circuits, pp. 87-90, 2000. [40] Yuan, J. Svensson, C., 'High-speed CMOS circuit technique,' IEEE J. Solid-State Circuits , vol.24, no.1, pp. 62-70, Feb. 1989. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25992 | - |
dc.description.abstract | 隨著高速數位存取介面迅速的發展,連接主要裝置與外部裝置的高速串列式連結越來越受歡迎,例如Serial AT Attachment (SATA)是最先進的外部儲存介面之一,傳輸速率已經高達3Gbps以上,在不久將來更會達到6Gps。但伴隨愈高速的傳輸速率,訊號會帶來更嚴重的電磁干擾。因此SATA系統需要能以調變頻率30KHz ~33KHz向下展頻5000ppm來降低電磁干擾。
展頻是一種犧牲訊號的完整性來降低電磁干擾的特殊技巧。因為電磁干擾與時脈抖動(jitter)是一個取捨的關係,因此本論文提出一個特別的方法能降低電磁干擾效應且能兼顧時脈完整性的展頻時脈產生器(spread spectrum clock generator,SSCG)。除了在頻域的電磁干擾衰減量,考慮展頻時脈在時域上所造成的影響才是更重要的部分因為在串列資料傳輸的過程中訊號在時域上的完整性是非常重要的議題。 我們使用互補式金氧半電晶體0.18μm的製程來設計晶片,本論文提出一個具有可程式控制展頻量的展頻時脈產生器,此技術是利用儲存在上下數計數器的數位資料來控制展頻量,而上下數計數器的時脈是由一低頻的整數-N頻率合成器來提供,使得調變頻率可維持在一個定值,因此我們可依系統需求來動態地調變展頻量使得在電磁干擾與時脈抖動之間可得一組最佳的值。 | zh_TW |
dc.description.abstract | As external storage devices are widely used, high-speed serial links connection host and external devices are becoming popular. Serial AT Attachment (SATA.) is one of the most promising technologies providing large bandwidth up to 3Gb/s with possible extension to 6Gb/s in the near future. As operating a high speed data rate, currents and voltages present in the circuit and the signal traces lead to great Electro-Magnetic Interference (EMI), Therefore, SATA systems require a wide spreading of 5000ppm and a 30~33KHz modulation rate to reduce EMI.
Spread spectrum is a special frequency modulation technique, which is sacrificed the signal integrity of the clock to reduce the EMI. In this thesis, we proposed a novel spread spectrum clock generator (SSCG) to release the trade-offs between the jitter performance and the amount of EMI reduction for SATA appications. Besides considering the amount of EMI peak reduction in frequency-domain, it is more important to take care of the impact in time-domain for SSCGs since the signal integrity in time-domain is a very significant issue for serial data transmissions. This chip is implemented in the process of 0.18um CMOS. In chapter 4 we proposed a programmable triangular generator technique for SSCG (Down spread 2500ppm~ 5000ppm). The technique utilizes the digital data stored in up/down counter to control the spread spectrum amount. An integer-N frequency synthesizer (low frequency) supplies the up/down counter clock to maintain the modulation frequency. Therefore we can adjust spread spectrum amount dynamically to achieve an optimal value between EMI reduction amount and the performance of jitter. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:58:09Z (GMT). No. of bitstreams: 1 ntu-98-R95943094-1.pdf: 4888709 bytes, checksum: 8b57a82de1ce758a276771e3e874ac99 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 論文審定書(中文)………………………………………………………………………i
論文審定書(英文)………………………………………………………………………iii 誌謝………………………………………………………………………………………v 中文摘要………………………………………………………………………………vii Abstract…………………………………………………………………………………ix 目錄……………………………………………………………………………………xi 圖片目錄………………………………………………………………………………xiv 表格目錄……………………………………………………………………………xviii 第一章 緒論………………………………………………………………………… 1 1.1 動機………………………………………………………………………… 1 1.2 論文架構…………………………………………………………………… 5 第二章 展頻時脈產生器之基本觀念……………………………………………… 6 2.1減少電磁干擾效應之技巧……………………………………………… 6 2.2 展頻之基本原理…………………………………………………………… 9 2.2.1 觀念…………………………………………………………………… 9 2.2.2 展頻模式及展頻量………………………………………………… 12 2.2.3 調變頻率……………………………………………………………… 13 2.2.4 調變波形……………………………………………………………… 14 2.2.5 時間域影響…………………………………………………………… 16 2.2.5.1週期至週期時間動……………………………………………… 17 2.2.5.2長時期時間抖動………………………………………………… 18 2.3 使用展頻時脈的考量……………………………………………………… 19 2.4 展頻時脈產生器的調變方式與架構……………………………………… 21 第三章 使用三角積分調變的分數式頻率合成器………………………………… 25 3.1鎖相迴路的基本原理……………………………………………………… 26 3.2 鎖相迴路的分析…………………………………………………………… 26 3.2.1 相位頻率偵測器與回路濾波器……………………………………… 27 3.2.2 電壓控制振盪器……………………………………………………… 29 3.2.3 鎖相迴路的線性模型………………………………………………… 29 3.2.4 鎖相迴路的相位雜訊………………………………………………… 31 3.3 分數式頻率合成器………………………………………………………… 33 3.3.1 脈波移除……………………………………………………………… 33 3.3.2 小數突波……………………………………………………………… 35 3.4 三角積分調變器…………………………………………………………… 37 3.5 MASH 1-1-1三角積分調變器……………………………………………… 39 第四章 可程式三角波調變的展頻時脈產生器…………………………………… 43 4.1 展頻時脈產生器在除頻器調變的架構…………………………………… 43 4.1.1 傳統對除頻器做調變的展頻時脈產生器……………………………… 44 4.1.2 所提出可程式三角波調變的展頻時脈產生器……………………… 46 4.2 線性模型與參數設計……………………………………………………… 50 4.2.1 行為模擬………………………………………………………………… 52 4.3 電路組成元件……………………………………………………………… 58 4.3.1可讀出資料的SIPO介面架構…………………………………………59 4.3.1.1 SIPO介面…………………………………………………………60 4.3.1.2 SIPO之Control Logic……………………………………………… 61 4.3.1.3 樹狀解碼器(Tree Decoder)………………………………………62 4.3.2 可程式化的三角波調變器…………………………………………… 63 4.3.2.1 比較器(Comparator)………………………………………………65 4.3.2.2 整數型式頻率合成器………………………………………………66 4.3.3 產生3GHz~2.985GHz的分數式頻率合成器…………………………73 4.3.3.1電荷幫浦電路與偏壓部分…………………………………………73 4.3.3.2 MASH 1-1-1…………………………………………………………74 4.3.3.3三階迴路濾波器……………………………………………………74 4.3.3.4 3GHz的壓控振盪器…………………………………………………75 4.3.3.5預除器(Prescaler)……………………………………………………76 4.4模擬設定與結果………………………………………………………………79 4.4.1可讀出資料的SIPO介面架構………………………………………79 4.4.2可程式化三角波調變器………………………………………………80 4.4.2.1頻率合成器(276MHz~552MHz)…………………………………80 4.4.2.2計數邏輯控制與10位元的上下數計數器………………………82 4.4.3產生3GHz~2.985GHz的分數式頻率合成器…………………………83 4.4.3.1相位頻率偵測器…………………………………………………83 4.4.3.2 3GHz的壓控振盪器………………………………………………84 4.4.3.3未展頻的展頻時脈產生器模擬圖………………………………84 4.4.3.4向下展頻5000ppm的SSCG模擬圖……………………………85 4.4.3.5向下展頻2500ppm的SSCG模擬圖……………………………86 4.4.3.6可程式展頻量的SSCG整體比較………………………………86 4.5 實驗結果………………………………………………………………………87 4.5.1晶片佈局………………………………………………………………88 4.5.2量測環境設定…………………………………………………………89 4.5.3印刷電路板製作………………………………………………………90 4.5.4量測結果………………………………………………………………91 4.5.5量測結果探討…………………………………………………………92 第五章 總結與展望……………………………………………………………………97 5.1 總結…………………………………………………………………………… 97 5.2 展望…………………………………………………………………………… 98 參考文獻……………………………………………………………………………… 99 | |
dc.language.iso | zh-TW | |
dc.title | 可程式化三角波調變的展頻時脈產生器 | zh_TW |
dc.title | A Spread Spectrum Clock Generator For SATA With Programmable Triangular Modulator | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊?頡,翁若敏,黃崇禧,楊清淵 | |
dc.subject.keyword | 展頻時脈產生器,可程式化三角波調變器,上下數計數器,電磁干擾,整數-N頻率合成器, | zh_TW |
dc.subject.keyword | Spread Spectrum Clock Generator,programmable triangular generator,Up/Down counter,Electro-Magnetic Interference,integer-N frequency synthesizer, | en |
dc.relation.page | 102 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-07-10 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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