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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25901完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳家麟(Ja-Ling Wu) | |
| dc.contributor.author | Yen-Lin Huang | en |
| dc.contributor.author | 黃彥霖 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:56:50Z | - |
| dc.date.copyright | 2009-07-23 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-21 | |
| dc.identifier.citation | [1] Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Recommendation H.264 and ISO/IEC 14496-10 Std., 2003.
[2] J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, and T. Wedi, “Video Coding With H.264/AVC: Tools, Performance, and Complexity,” IEEE Circuit and Systems Magazine, vol.4, no. 1, pp. 7-28, 2004. [3] Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Recommendation H.264 and ISO/IEC 14496-10 / Amd.3 Scalable video coding Std., 2007. [4] M. Wien, H. Schwarz, and T. Oelbaum, “Performance Analysis of SVC,” IEEE Transactions on Circuits and Systems for Video Technology, May, 2007. [5] J. Vieron, M. Wien, and H. Schwarz, “JSVM 9 Software”, Dec. 2008. [6] Owens, J.D.; Houston, M.; Luebke, D.; Green, S.; Stone, J.E.; Phillips, J.C., “GPU Computing”, Proceedings of the IEEE, Vol 96, Issue 5, pp. 879-899, May 2008. [7] Heiko Schwarz, Detlev Marpe, and Thomas Wiegand, “Overview of the Scalable Video Coding Extension of the H.264/AVC Standard”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 9, pp. 1103-1120, Sep. 2007. [8] NVIDIA, “NVIDIA CUDA Compute Unified Device Architecture Programming Guide”, Version 2.1, 2008. [9] Tourapis, H.-Y.C.; Tourapis, A.M., “Fast motion estimation within the H.264 codec”, ICME 2003, July 2003. [10] NVIDIA, “CUDA CUBLAS library”, Sep 2008. [11] Shu-Sian Yang, Ja-Ling Wu, “Design and Implementation of H.264/MPEG4-AVC Scalable Extension Encoder on Multi-Core Processors” , June, 2007, master thesis of department of CSIE, NTU. [12] X. Zhou, E. Li, and Y. Chen, “Implementation of H.264 Decoder on General-Purpose Processors with Media Instructions,” In Proceedings of SPIE Conference on Image and Video Communications and Processing, vol. 5022, pp. 224-235, 2003. [13] S. Warrington, H. Shojania, S. Sudharsanan, and W. Chan, “Performance Improvement of the H.264/AVC Deblocking Filter Using SIMD Instructions,” In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ‘06), pp. 2697-2700, May 2006. [14] Mathias Wien , “Variable Block-Size Transforms for H.264/AVC”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 604-613, Jul. 2003. [15] T. Wiegand, G.J. Sullivan, G. Bjntegaard, and A. Luthra, “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 560-576, Jul. 2003. [16] T. Wedi and H. Musmann, “Motion- and Aliasing-Compensated Prediction for Hybrid Video Coding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 577-586, 2003. [17] Wei-Nien Chen, Hsueh-Ming Hang, “H.264/AVC motion estimation implementation on Compute Unified Device Architecture (CUDA)”, ICME 2008, pp. 697-700. [18] Man Cheung Kung, Oscar C. Au, Peter H. W. Wong, Chun-Hung Liu: “Intra Frame Encoding Using Programmable Graphics Hardware”, PCM 2007: 609-618. [19] H. Schwarz, D. Marpe and T. Wiegand, “Inter-layer Prediction of Motion and Residual Data,” ISO/IEC JTC1/SC29/WG11 Doc. M11043, Jul. 2004. [20] H. Schwarz, T. Hinz, D. Marpe, and T. Wiegand, “Constrained Inter-Layer Prediction for Single-Loop Decoding in Spatial Scalability,” In Proceedings of IEEE International Conference on Image Processing (ICIP '05), vol. 2, pp. 870-873, Sep. 2005. [21] I. Richardson, “H.264 and MPEG-4 Video Compression,” Wiley, 2003. [22] E.B. van der Tol, E.G. Jaspers, and R.H. Gelderblom, “Mapping of H.264 Decoding on a Multiprocessor Architecture,” In Proceedings of SPIE Conference on Image and Video Communications and Processing, vol. 5022, pp. 707-718, 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25901 | - |
| dc.description.abstract | 可調式視訊編碼 (Scalable Video Coding, SVC) 是針對需要傳輸或儲存多樣空間與時間解析度之影片的多媒體系統所設計，能藉由簡單地截去當前時間與空間解析度所不需要的位元流達成目標解析度影片之重建，同時並利用精細可調式編碼 (Fine Grain Scalability, FGS) 提供品質調整以適應頻道頻寬之變化。
在H.264/MPEG4-AVC 視訊編碼標準完成後，可調式視訊編碼成為 ISO/IEC MPEG 與 ITU-T VCEG 合組之聯合視訊小組 (Joint Video Team, JVT) 進行標準化之主要目標。在目前的設計中，多數H.264/MPEG4-AVC 所採用之先進編碼工具將被保留以達成基本層 (Base Layer) 的向後相容，此外，可調性與編碼效率間的取捨亦達到平衡，其 PSNR 值僅較傳統H.264/MPEG4-AVC 下降約 1 dB。 隨著多處理器系統的逐漸普及與多執行緒函示庫的成熟，平行處理被視為下個世代視訊編碼器的主流。然而傳統的單執行緒視訊編碼器並無法利用多處理器系統的優勢。我們基於可調式視訊編碼中的動態補償所設計的平行處理演算法，提供較傳統演算法更高的運算速度。 | zh_TW |
| dc.description.abstract | The scalable video coding (SVC), an extension of H.264/MPEG4-AVC, was standardized in 2007 by Joint Video Team (JVT) of the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group. SVC provides spatial, temporal and SNR scalabilities to serve multimedia systems or devices with various resolution, quality and computing power requirement. To achieve these three scalabilities, SVC uses additional coding tools and coding modes based on H.264/MPEG4-AVC, and most components of H.264/MPEG4-AVC are adopted in SVC design to allow the base layer of an SVC bit-stream can be decoded by any H.264/MPEG4-AVC compliant decoder. The coding tools used by SVC and the variety coding modes decision make the corresponding coding complexity become extremely high, so real-time realization of SVC is nearly impossible by using software and single-core CPU only. One possible solution to generate SVC streams in time is to parallelize the whole encoding process. Currently, multi-core CPU and GPU are two popular kinds of parallel processing architectures. Not much research has been devoted to realize the parallel SVC encoders based on the co-work of these two architectures. In this thesis, a scalable computation model for spatial SVC using multi-core CPU and GPGPU through NVIDIA CUDA is proposed. On the basis of the proposed computational model, a solution to solve the challenging data transition problem of this CPU-GPU co-work architecture is then provided. Simulation results show that, through our work, significant speed up gain in spatial SVC encoding can be achieved. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:56:50Z (GMT). No. of bitstreams: 1 ntu-98-R96922036-1.pdf: 2527798 bytes, checksum: 4cc45276963af2bc76c34073f91d9caa (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Chapter 1 1
Introduction 1 1.1 H.264/MPEG4-AVC and H.264/MPEG4-AVC Scalable Extension 1 1.2 Parallel Video Encoding 4 1.3 Related Work 9 1.4 Thesis Organization 10 Chapter 2 12 Accelerating H.264/MPEG4-AVC Coding Tools by Using NVIDIA CUDA Based Scalable Computation 12 2.1 Overview of NVIDIA Compute Unified Device Architecture (CUDA) 12 2.1.1 Hardware Architecture 12 2.1.2 Programming and Execution Model 14 2.1.3 Performance Tuning of CUDA Programs 15 2.1.3.1 Maximum Number of Threads per Block 15 2.1.3.2 Parallel Reduction 16 2.1.3.3 Memory Coalescing – Access Pattern 20 2.1.3.4 Loop Unrolling 21 2.2 H.264/MPEG4-AVC Coding Tools Acceleration 22 2.2.1 Temporal Domain Prediction 25 2.2.2 Spatial Domain Prediction 28 2.3 Proposed H.264/MPEG4-AVC Encoder Modification 31 2.3.1 The CPU-GPU (Host-Device) Co-working Model and Data Transition Problem 31 2.3.2 H.264/MPEG4-AVC Encoder Modification 34 Chapter 3 38 Multi-core CPU Based Spatial SVC Coding Mode Decision 38 3.1 Decision Tree for Spatial SVC Base Layer and Enhancement Layer Coding Modes 41 3.2 Coding Mode Trees from Single-core to Multi-core CPU Based Computation 44 3.2.1 Single-core CPU 44 3.2.2 Quad-core CPU 44 3.2.3 Dual-core CPU 47 Chapter 4 49 Experimental Results 49 4.1 Speed up Performance of the H.264/MPEG4-AVC Baseline Encoder 51 4.2 Speed up Performance of the Spatial H.264/MPEG4-AVC Scalable Extension Encoder 54 Chapter 5 56 Conclusions and Future Work 56 5.1 Conclusions 56 5.2 Future Work 57 Bibliography 58 | |
| dc.language.iso | en | |
| dc.title | 多核心以及CUDA架構下空間性可調式視訊編碼器之可調式計算 | zh_TW |
| dc.title | Scalable Computation for Spatially Scalable Video Coding Using NVIDIA CUDA and Multi-core CPU | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳恆佑(Herng-Yow Chen),朱威達(Wei-Ta Chu),薛智文(Chih-Wen (Steven) | |
| dc.subject.keyword | 視訊編碼,先進視訊編碼,可調式視訊編碼,跨層估測,快速移動估測,平行演算法, | zh_TW |
| dc.subject.keyword | Video coding,H.264/MPEG4-AVC,Scalable Video Coding (SVC),GPU,Multi-core,CUDA,parallel computing, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-07-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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