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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25820
標題: | 具有一個新穎補償方式的循漸近式逼近類比數位轉換器 A New Calibration Method for Successive Approximation Register A/D Converter |
作者: | Hung-Wei Kevin Chen 陳宏維 |
指導教授: | 陳信樹(Hsin-Shu Chen) |
關鍵字: | 類比數位轉換器,循漸近式逼近, A/D converter,ADC,SAR,successive approximation register, |
出版年 : | 2006 |
學位: | 碩士 |
摘要: | 近年來低功率的電子產品的需求是越來越重要,特別是應用於無線和感應器系統中•類比數位轉換器是此類系統中的重要原件,所以如何降低類比數位轉換器的耗電是一個熱門的研究題目•目前在感應器系統中主流的類比數位轉換器架構為電荷重新分佈式的循漸近式逼近法•在某些感應器應用裡需要一個較高解析度的類比數位轉換器•但是這架構的精準度通常只有到10位元其主要原因為電容之間的匹配誤差•加上校正電路後精準度是可以提高的,但是過去所提出的校正電路是很耗電的•本論文提出一個切換式電容的校正電路,可以提高精準度但是只耗少許的電•電荷重新分佈式的循漸近式逼近法轉換器架構於電荷守衡定律,電容陣列之間的匹配誤差會使在比較過程造成電壓的漂移•本校正電路基本的想法是在取樣的時候儲存固定的正或負電荷於校正電容裡,然後在比較過程中依據匹配誤差的量,把儲存的電荷在加進電容陣列中來校正電壓的漂移•本設計實現於TSMC 0.35μm CMOS的製程•晶片的面積為1.88x1.88mm2,類比數位轉換器核心面積為0.83 x 0.74mm2•轉換速度為每秒鐘20萬次•類比電路所量測到的耗電為1.35毫瓦在5伏特電工作電壓,數位電路所量測到的耗電為3.3毫瓦在3.3伏特電工作電壓•在動態精準度的量測值,自我校正前SNDR為63.9dB,SFDR為74.7dB•自我校正後SNDR為47.9dB,SFDR為50.6dB•在自我校正後準確度卻下降,這跟預期不同•其原因為測試電路上的吵雜環境•但是校正電路所影響的只有在單數諧的諧波,這跟理論推導是相同的• The demand of low power electronic device is become strongly these years, especially in wireless and sensor network devices. Analog to digital converter (ADC) is the key building block of these devices. Therefore, a hot research topic is to reduce ADC power consumption. For some sensor application, the highly accuracy ADC is required. A main ADC architecture for sensor application is success approximation register (SAR). It’s accuracy is usually limited by the mismatch of capacitor array which is about 10 bit. A calibration circuit can be added to enhance the accuracy; however, it usually dissipates a lot power. This work presents a switch capacitor calibration technique to enhance the performance without consume a lot of power. The charge redistribution SAR ADC operation theory is base on charge conservation law. The mismatch of capacitor would cause the voltage shift during the comparison phase. The fundamental of this calibration idea is to store the positive and negative charge in the calibration capacitors during the sample phase. Then, during the comparison phase, these pre-stored charge injects into the main capacitor array to correct the voltage shift. This work is fabricated by TSMC 0.35um CMOS technology. The chip area is 1.88x1.88mm2, and the core area is 0.83 x 0.74mm2. The conversion rate is 200KS/s, and the measured analog power is 1.35mW at 5V and digital power is 3.3mW at 3.3V. The SNDR and SFDR before self-calibration are 63.9 and 74.7dB. After self-calibration process the SNDR and SFDR are 47.9 and 50.6dB. The performance after self calibration is degraded, and it is not expected. The cause of degrading may be noisily environment of testing board. However, the effect of this calibration circuit is only in odd harmonic, and it is the same as the prediction. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25820 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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