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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25759完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Yi-Pei Su | en |
| dc.contributor.author | 蘇逸霈 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:28:36Z | - |
| dc.date.copyright | 2006-07-31 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-26 | |
| dc.identifier.citation | [1] Application Note of “AN634, Pipeline ADCs Come of Age” Maxim Inc., 2000.
[2] Data sheet of “AD9887, dual interface for flat panel displays,” Analog Devices Inc., 2001. [3] R.V.D. Plassche, “Integrated Analog-to-Digital and Digital-to-Analog Converters” Kluwer Academic Publishers, 1994 [4] B.Razavi, “Principles of Data Conversion System Design” IEEE Press 1995 [5] T. Cho and P. R. Gray, “A 10 b 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995 [6] F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 853–863, Nov. 1995. [7] Yuh-Min Lin, Beomsup Kim and Paul R. Gray,” A 13-b 2.5-MHz Self-calibrated Pipelined A/D Converter in 3-μm CMOS ,” IEEE J. Solid‐State Circuits, vol. 26, no. 4, pp. 628-636, Apr. 1991 [8] S. Sutarja et al., “A 250 ks/s 1% pipelined A/D converter,” in ISSCC Dig. Tech. Papers, 1988, pp. 228-229. [9] B.-S. Song et al., “A 12b 1 MHz capacitor error averaging pipelined A/D converter,” in ISSCC Dig. Tech. fapen, 1988, pp.226-227 [10] B.-S. Song, M. Tompsett, and K. Lakshmikumar,” A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D Converter,” IEEE J. Solid‐State Circuits, vol. 23 no. 6, pp. 1324-1333, Dec. 1988 [11] Hsin-Shu Chen, Bang-Sup Song , and Kantilal Bacrania ,” A 14-b 20-MSample/s CMOS Pipelined ADC,” in ISSCC Dig. Tech. Papers, 2001 [12] Hsin-Shu Chen, Bang-Sup Song , and Kantilal Bacrania ,” A 14-b 20-MSample/s CMOS Pipelined ADC,” IEEE J. Solid‐State Circuits, vol. 36, no. 6, pp.997-1001, Jun. 2001 [13] Hsin-Shu Chen, “ High-resolution nyquist-rate analog-to-digital converter,” Ph.D. dissertation, Univ. of Illinois at Urbana-Champaign, 2001 [14] T. Matsuura, T. Nara, T.Komatsu, E. Imaizumi, T. Matsutsuru, R. Horita, H. Katsu, S. Suzumura, and K. Sato, “A 240-Mb/s 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 33, pp. 1840–1850, Nov. 1998. [15] S. H. Lewis and P. R. Gray, “A pipelined 5MS/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, 1987. [16] A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1207–1215, Dec. 1993. [17] S.H. Lewis, H.S. Fetterman, G. F. Gross, Jr., R. Ramchandran, and T.R. Viswanathan, “A 10–b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [18] W.Song, H.Choi, S. Kwak, and Bang-Sup Song ,” A 10-b 20-MSample/s low-power CMOS ADC,” IEEE J. Solid‐State Circuits, vol. 30, pp.514-521, May 1995 [19] P.R. Gray and R.G.Meyer, Analysis and design of Analog Integrated Circuits, 3rd ed. New York: John Wiley & Sons, Inc., 1993 [20] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers,” Matching properties of MOS transistors,” IEEE J. Solid‐State Circuits, vol. 24, pp.1433-1400, Oct. 1989 [21] S.J.Lovett, M. Welten, A.Mathewson, and B. Mason, “ Optimizing MOS transistor mismatch,” IEEE J. Solid‐State Circuits, vol. 33, pp.147-150, Jan. 1998. [22] M.Pelgrom et al., “Matching properties of MOS transistors”, IEEE Joumal of Solid-State Circuits, vo1.24, nos, pp1433- 1439, 1989 [23] M. Steyaert, V. Peluso, J. Bastos, P. Kinget and W. Sansen, “Custom Analog Low Power Design: The problem of low voltage and mismatch,” in Proc. IEEE 1997 Custom Integrated Circuits Conf., 1997, pp. 13.1.1-13.1.8 [24] D. J. Foley, and M. P. Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp 417-423, March 2001. [25] S. Kim, K. Lee, Y. Moon, D. K. Jeong, M. K. Kim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE Journal of Solid-state Circuits, vol. 32, no. 5, pp. 691-700, May 1997. [26] J. G. Maneatis, “precise delay generation using coupled oscillators,” Ph. D. dissertation, Stanford University, June 1994. [27] H.W. Ott, Noise Reduction Techniques in Electronic Systems, 2nd ed, NEW York: Yhon Wiley & Sons, Inc., 1988 [28] J. Doernberg, H. S. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE Journal of Solid-State Circuits, vol. 19,pp.820-827, Dec. 1984. [30] Andrew M. Abo and Paul R. Gray,” A 1.5V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter,” IEEE J. Solid‐State Circuits, vol. 34, no. 5, pp. 599-606, May 1999 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25759 | - |
| dc.description.abstract | 隨著無線通訊系統及各種手提式消費電子產品盛行，對於具備高速及高解析度積體電路的需求已經是不可或缺。雖然現今的許多應用產品都是利用數位信號處理 (DSP) 來解決傳送訊號的問題，但是在接收到的訊號及數位信號處理系統之間仍然需要一個類比/數位的轉換介面，也因此類比/數位轉換器便扮演了一個重要的角色。
這篇論文中，我們運用電容錯誤平均技術結合前瞻決定技巧 (capacitor error-averaging technique with look-ahead decision) 實現了一個高解析度、高速的管線式類比/數位轉換器。電容錯誤平均技術在時脈上需要三個相位(傳統的管線式類比/數位轉換器僅需要兩個相位)，在速度上會有所限制。但前瞻決定技巧若應用在三個相位的系統上卻恰好能夠使得放大器擁有一整個相位的時間來讓輸出值穩定(settle) (傳統的管線式類比/數位轉換器只能利用一部分的相位)。為了要產生所需要的三個相位，我們在晶片中使用了兩種不同的時脈產生器。其中一種是由二進位計數器及非重疊電路所組成。另一種是由延遲鎖相迴路組成。 這兩顆類比/數位轉換器都是使用 TSMC 0.35 μm, 5-V, 2P4M 互補式金氧半製程。使用二進位計數器的類比/數位轉換器，它的 DNL 為 +1.12 / - 1 LSB，INL 為 + 4.63/ -4.63 LSB，SNR 為 68.48 dB，THD 為 78.03 dB，SNDR 為 68.03 dB。使用延遲鎖相迴路的類比/數位轉換器，它的 DNL 為 +1.12 / - 1 LSB，INL 為 + 4.63/ -4.63 LSB，SNR 為 68.48 dB，THD 為 78.03 dB，SNDR 為 68.03 dB。它們的面積分別為 10.8 mm2。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:28:36Z (GMT). No. of bitstreams: 1 ntu-95-R92943084-1.pdf: 6174754 bytes, checksum: d3c38b50d1595829ea17cb3fda6841d4 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 摘要………………………………………………………………...…………….....i
Abstract......................................................................................................................ii Table of Contents.......................................................................................................iii List of Figures............................................................................................................v List of Tables.............................................................................................................vii Chapter1 Introduction.............................................................................................1 1.1 Motivation and Goal................................................................................1 1.2 Application of Analog-to-Digital Converters...........................................2 1.2.1 CCD Imaging System……………………………………………….2 1.2.2 LCD Monitor Controller System……………………………………3 1.3 Thesis Organization …………………………………………………….4 Chapter 2 Fundamentals of Analog- to-Digital Converter....................................6 2.1 Introduce…………………………………..............................................6 2.2 ADC Performance Metrics……………………......................................7 2.2.1 Differential Nonlinearity (DNL)…………………………………....7 2.2.2 Integral Nonlinearity (INL)…………………………………………8 2.2.3 Offset Error………………………………………………………..10 2.2.4 Gain Error…………………………………………………………10 2.2.5 Signal-to-Noise Ratio (SNR)……………………………………...10 2.2.6 Total Harmonic Distortion (THD)………………………………...11 2.2.7 Spurious-Free Dynamic Range (SFDR)…………………………..11 2.2.8 Signal-to-Noise and Distortion Ratio (SNDR)……………………12 2.2.9 Effective Number of Bits (ENOB)………………………………...12 2.2.10 Dynamic Range (DR)……………………………………………..13 2.3 Review of ADC Architecture.......... ...............................................13 2.3.1 Flash ADC Architecture...................................................................14 2.3.2 Successive Approximation Register (SAR) ADC............................16 2.3.3 Subranging ADC..............................................................................17 2.3.4 Time Interleaved ADC.....................................................................18 2.3.5 Pipelined ADC…………………………………………………….20 2.4 Summary……………………………………………………………..22 Chapter 3 Capacitor Error-Averaging with Look-Ahead Decision...................23 3.1 Introduction of Pipelined ADC..............................................................23 3.2 Error Sources in Pipelined ADC............................................................25 3.3 Capacitor Error-Averaging.....................................................................29 3.4 Capacitor Error-Averaging with Look-Ahead Decision Technique.......35 3.4.1 Look-Ahead Decision Technique.....................................................35 3.4.2 Capacitor Error-Averaging with Look-Ahead Decision Technique..42 Chapter 4 Design of Pipelined Analog-to-Digital Converter .........................46 4.1 Introduction............................................................................................46 4.2 High Level System Design.....................................................................46 4.3 Building Blocks Design………………………......................................47 4.3.1 Sample-and-Hold Amplifier (SHA)………………………………..47 4.3.2 Multiplying Digital-to-Analog Converter (MDAC)……………….49 4.3.3 Operational Amplifier……………………………………………...51 4.3.4 Bias circuit…………………………………………………………54 4.3.5 Flash Analog-to-Digital Converter (Sub-ADC)……………………56 4.3.5.1 Capacitive reference voltage divider………………………...56 4.3.5.2 Comparator…………………………………………………..57 4.3.6 Three Phase Delay-Locked Loop (DLL)-Based Clock Generator……63 4.3.6.1 Conventional DLL …………………………………………..65 4.3.6.2 Self-Correcting DLL…………………………………………67 4.3.6.3 False Lock Detector………………………………………….68 4.3.6.4 Phase Frequency Detector (PFD)……………………………69 4.3.6.5 Charge Pump (CP)…………………………………………...69 4.3.6.6 Bias Circuit…………………………………………………..70 4.3.6.7 DLL Simulation……………………………………………...70 Chapter 5 Test Setup and Experimental Results.....................................................72 5.1 Test Setup..................................................................................................72 5.2 Evaluation Board Design………………………………………………..74 5.3 Experimental Results................................................................................82 5.3.1 Static Test............................................................................................84 5.3.2 Dynamic Test.......................................................................................86 5.4 Summary....................................................................................................91 Chapter 6 Conclusion………………………….........................................................93 6.1 Conclusion.................................................................................................93 Bibliography………...………………………….........................................................94 | |
| dc.language.iso | en | |
| dc.subject | 類比/數位轉換器 | zh_TW |
| dc.subject | analog-to-digital converter | en |
| dc.title | 一個具有延遲鎖相迴路時脈產生器的類比/數位轉換器 | zh_TW |
| dc.title | An Analog-to-Digital Converter with DLL Clock Generator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 顧孟愷(Mong-kai Ku),洪士灝(Shih-Hao Hung),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 類比/數位轉換器, | zh_TW |
| dc.subject.keyword | analog-to-digital converter, | en |
| dc.relation.page | 96 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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