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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Shao-Hung Lin | en |
dc.contributor.author | 林紹弘 | zh_TW |
dc.date.accessioned | 2021-06-08T06:12:21Z | - |
dc.date.copyright | 2007-07-16 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-06-29 | |
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Lee, “High-Speed Circuit Designs for Transmitters in Broadband Data Links,” IEEE JSSC, vol. 41, pp. 1004–1015, May. 2006. [2.4] H. Nosaka, etc. “A 39-to-45-Gbit/s Multi-Data-Rate Clock and Data Recovery Circuit With a Robust Lock Detector,” IEEE JSSC, vol. 39, pp. 1361-1365, Aug. 2004. [2.5] J. Savoj and B. Razavi, “A 10Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Linear Phase Detector,” IEEE JSSC, vol. 36, pp. 761-767, May 2001. [2.6] S. B. Anand and B. Razavi, “A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data,” IEEE JSSC, vol. 36, pp. 432–439, Mar. 2001. [2.7] M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission Systems,” IEEE J. Solid-State Circuits, vol. 35, pp. 1992–1995, DEC 2000. [2.8] J. Savoj and B. Razavi, “A 10Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector,” IEEE JSSC, vol. 38, pp. 13-21, Jan 2003. [2.9] J. Lee, B. Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology,” IEEE JSSC, vol. 38, pp. 2181–2190, DEC. 2003. [2.10] M. Ramezani and C. Salama, “A 10Gb/s CDR with a half-rate bang-bang phase detector”, Proceedings of International Symposium on Circuits and Systems, vol. 2 , pp. II 181-184, May 2003. [2.11] M. H. Perrott, Y. Huang, R. T. Baird, B. W. Garlepp, D. Pastorello, E. T. King, Q. Yu, D. B. Kasha, P. Steiner, L. Zhang, J. Hein, B. D. Signore, “A 2.5-Gb/s Multi-Rate 0.25-μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-digital Referenceless Frequency Acquisition,” IEEE J. Solid-State Circuits, vol. 41, pp. 2930–2944, DEC 2006. [2.12] F.M. Gardner, “Properties of frequency difference detectors,” IEEE Trans. Commun., vol. 33, pp. 131-138, Feb. 1985. [2.13] D. G. Messerschmitt, “Frequency detectors for PLL acquisition in timing and carrier recovery,” IEEE Trans. Commun., vol. 27, pp. 1288-1294, Sep. 1979 [2.14] C. G. Yoon, S. Y. Lee and C. W. Lee, ”Digital logic implementation of the quadricorrelators frequency detector,” in Proc. IEEE 37th Midwest Symposium on Circuits and Systems, vol. 2, Aug. 1994, pp.757-760. [2.15] B. Stilling, “Bit rate and protocol independent clock and data recovery,” Electronics Letters, vol. 36, pp. 824–825, April 2000. [2.16] T.H. Toifl and P. Moreira, “Simple frequency detector circuit for biphase and NRZ clock recovery,” Electronics Letters vol. 34, no. 20, pp. 1922-1923, Oct 1998 [2.17] R. J. Yang, K. H. Chao, and S. I. Liu, “A 200Mbps~2Gbps continuous-rate clock and data recovery circuit,” IEEE Transactions on circuits and systems, Part-I: regular papers, vol. 53, pp. 842-847, April 2006. [2.18] R. J. Yang, K. H. Chao, S. C. Hwu, C. K. Liang, and S. I. Liu, “A 155.52Mbps~ 3.125Gbps continuous-rate clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 41, pp. 1380–1390, June 2006. [3.1] R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Trasmission Systems”, pp.34-pp.45, Phase-Locking in High-Performance System, IEEE press, 2003, ISBN 0-471-44727-7 [3.2] M. Ramezani, C. Andre, and T. Salama, “Analysis of a Half-Rate Bang-Bang Phase-Locked-Loop”, IEEE Transactions on Circuits and Systems, vol. 49, pp.505-509, no.7, July 2002 [3.3] N. D. Dalt, “A Design-Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs”, IEEE Transactions on Circuits and Systems, vol. 52, pp.21-31, no.1, Jan. 2005 [3.4] J. Lee, K. S. Kundert, and B. Razavi, “Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits,” IEEE Custom Integrated Circuits Conference, pp.711-714, Sept. 2003 [3.5] Y. Choi, D. K. Jeong, W. Kim, “Jitter Transfer analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery”, IEEE Transactions on Circuits and Systems, vol.50, pp. 775-783, no.11, Nov. 2003 [4.1] J. D. H. Alexander, “Clock recovery from random binary data,” Electronics Letters, vol. 11, pp. 541–542, Oct. 1975. [4.2] T. H. Toifl and P. Moreira, “Simple frequency detector circuit for biphase and NRZ clock recovery,” Electronics Letters, vol. 34, pp. 1922–1923, Oct. 1988 [4.3] R. J. Yang, K. H. Chao, and S. I. Liu, “A 200Mbps~2Gbps continuous-rate clock and data recovery circuit,” IEEE Transactions on circuits and systems, Part-I: regular papers, vol. 53, pp. 842-847, April 2006. [4.4] R. J. Yang, K. H. Chao, S. C. Hwu, C. K. Liang, and S. I. Liu, “A 155.52Mbps~ 3.125Gbps continuous-rate clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 41, pp. 1380–1390, June 2006. [4.5] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “A 12.5Mb/s to 2.7Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” Dig. Tech. Papers in IEEE Int. Solid-State Circuits Conference, pp. 230-231, Feb. 2005. [4.6] B. Stilling, “Bit rate and protocol independent clock and data recovery,” Electronics Letters, vol. 36, pp. 824–825, April 2000. [5.1] B. Razavi, “Design of Analog CMOS Integrated Circuit,” McGRAW-HILL, pp. 553, 2001. [5.2] R. J. Yang, K. H. Chao, and S. I. Liu, “A 200Mbps~2Gbps continuous-rate clock and data recovery circuit,” IEEE Transactions on circuits and systems, Part-I: regular papers, vol. 53, pp. 842-847, April 2006. [5.3] A. R. Shahani, D. K. Shaeffer, S. S. Mohan, H. Samavati, H. R. Rategh, M. D. M. Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, M. A. Horowitz, and T. H. Lee, “Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection,” IEEE J. Solid-State Circuits, vol. 33, pp. 2232-2239, DECEMBER 1998. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25411 | - |
dc.description.abstract | 這篇論文主要是描述如何實現應用於連續性頻帶時脈資料回覆電路以及鎖相迴路中的頻率相位偵測器。為了要達到可以接收連續性頻帶的資料,本文提出具有大範圍頻率鎖定機制的頻率偵測器。此外,時脈資料回覆電路以及具有高參考頻率的鎖相迴路,通常需要搭配適合高頻操作的bang-bang相位偵測器。這篇論文總共分為六個章節,其中第一章及第六章為導論及結論,在第二章裡,將會介紹各種不同的頻率偵測器以及相位偵測器架構。
在第三章裡我們將分析bang-bang迴路。由於非線性的特性,bang-bang迴路在穩定性的表現上和線性迴路有很大的差別。整個系統設計的參數也將用非線性的模型和方程式推導出來。同時也將介紹時脈擾動轉移函數以及時脈擾動容忍度的分析。 第四章裡詳述了連續性頻帶時脈資料回覆電路的實作,其中應用了我們所提出的三個全速率相位頻率偵測器和一個半速率的相位頻率偵測器。利用bang- bang 相位偵測器的三狀態特性,只需要加入一個AND閘便可以實現單方向無限頻率鎖定的頻率相位偵測器。所提出的電路比傳統電路消耗更少的功率,另外還提供了多項優點:面積小,對時脈驅動器的負載小,三狀態輸出,自我回覆資料,以及很寬的頻率鎖定範圍等等。除此之外,頻率鎖定過程有很完整的理論分析,實驗結果和分析也非常吻合。三個連續性頻帶時脈資料回覆電路用0.18um標準互補式金氧半製程實現。實驗結果顯示這些電路可以接受622Mbps到3.125Gbps的資料且錯誤率都低於10-12。每個全速率的時脈資料回覆電路大約消耗60mW的功率,而主動元件的面積是0.1326mm2。半速率的脈資料回覆電路大約消耗80mW的功率,而主動元件的面積是0.09mm2。 在第五章裡我們提出了三個應用於bang-bang鎖相迴路中的全速率頻率相位偵測器。利用前一章的觀念,只要加入一個額外的NOR閘便可以實現具有雙方向大範圍的頻率偵測器。且提出的這些電路不像傳統頻率相位偵測器擁有重置路徑,所以操作頻率可以提升。這個鎖相迴路的頻率鎖定過程也有完整的理論推導,且推導結果和模擬結果相當吻合。為了驗證頻率相位偵測器的功能,一個2GHz的bang-bang鎖相迴路被用0.18um標準互補式金氧半製程實現。整個電路大約消耗30mW的功率,而整個晶片的面積是0.85 x 0.4 mm2。 | zh_TW |
dc.description.abstract | This thesis describes the implementation of the bang-bang phase/frequency detectors (PD&FD) used in continuous rate clock and data recovery (CDR) circuit and phase-locked loop (PLL) circuit. In order to achieve continuous rate receivable, FDs with wide frequency locking range are developed. The CDR system or PLL with high reference frequency incorporate the bang-bang phase detector, which is suitable for high speed operation. This thesis is divided into six chapters. Chapter 1 is the introduction. In chapter 2, the various architectures of PD and FD are described.
In chapter 3, the mathematical analysis of the bang-bang loop is presented. The non-linearly characteristic of the bang-bang loop makes the stability requirement differ a lot from the linear loop. Design parameters are also derived from the nonlinear model and equations. The jitter transfer and jitter tolerance function of the bang-bang loop is also introduced. In chapter 4, three full-rate BBPFDs and a half-rate BBPFD are presented for the continuous-rate CDR circuit. Based on the characteristic of tristate BBPDs, only adding an AND gate can realize the FD function which has unilateral wide frequency locking range. They consume less power than conventional methods and their architectures provide several advantages: small area, less loading on clock buffer, tri-state output, recovering data by itself, wide frequency locking range, etc. In addition, the analytical analysis for the frequency acquisition time has been derived. The experimental results are also given to verify the theoretical analysis. Three continuous-rate CDR circuits are implemented to demonstrate BBPFD’s function. They are fabricated in a standard 0.18 um CMOS process. Measurements show the receivable data rate from 622Mbps to 3.125Gbps and the all bit error rates are below 10-12. Each full-rate continuous-rate CDR circuit consumes about 60mW at 3.125Gbps and core area is 0.1326mm2. The half-rate continuous-rate CDR consumes about 80mW at 3.125Gbps and core area is about 0.09 mm2. In chapter 5, three full-rate BBPFDs are presented for the BBPLL circuit. Based on the BBPFDs proposed for CDR circuit, an extra NOR gate can realize a FD with bi-direction wide frequency locking range. The proposed BBPFDs eliminate the reset path, hence the operation speed is higher than conventional one. Their frequency locking process has already been analyzed theoretically, and the results match with simulation results. A 2GHz BBPLL is fabricated in a standard 0.18 um CMOS process to verify BBPFD’s function. The power consumption is 30mW, and the chip area is 0.85 x 0.4 mm2. Finally, chapter 6 is the conclusion. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:12:21Z (GMT). No. of bitstreams: 1 ntu-96-R94943021-1.pdf: 5593948 bytes, checksum: fc2fe8ef3bc233355c26d99707c4efd1 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | 1. Introduction …………………………………………………1
2. Phase/Frequency Detector ………………………………… 3 2.1 General Considerations of Phase Detector ………… 4 2.2 Phase Detectors for PLL………………………………… 8 2.3 Phase Detectors for CDR………………………………… 13 2.4 General Considerations of Frequency Detector …… 24 2.5 Frequency Detectors for PLL…………………………… 25 2.6 Frequency Detectors for CDR…………………………… 28 3. Bang-Bang Loop Analysis ……………………………………37 3.1 1st Order BBPLL…………………………………………… 38 3.2 2nd Order BBPLL…………………………………………… 41 3.3 Time-Domain Analysis …………………………………… 42 3.4 The Trajectory of BBPLL………………………………… 49 3.5 Jitter Transfer & Jitter Tolerance ………………… 58 4. Bang-Bang Phase/Frequency Detectors for Continuous-Rate CDR Circuits……………………………………………………… 65 4.1 Circuit Description……………………………………… 65 4.2 The Frequency Acquisition Time Analysis…………… 73 4.3 System Architecture and Building Blocks…………… 80 4.4 Behavior Verification and Experimental Results … 83 4.5 Performance Comparison ………………………………… 95 5. Bang-Bang Phase/Frequency Detectors for Phase-Locked Loop Circuits …………………………………………………… 97 5.1 System Architecture……………………………………… 97 5.2 Proposed BBPFDs…………………………………………… 98 5.3 Frequency Locking Range………………………………… 102 5.4 Frequency Acquisition Process………………………… 103 5.5 Simulation Results ……………………………………… 112 5.6 Layout and Performance Summary ……………………… 114 6. Conclusion …………………………………………………… 115 Bibliography……………………………………………………… 117 | |
dc.language.iso | en | |
dc.title | 二元相位頻率偵測器之設計與應用 | zh_TW |
dc.title | Design and Implementation of Bang-Bang Phase/Frequency Detectors | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李洪松,林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee),陳巍仁(Wei-Zen Chen) | |
dc.subject.keyword | 鎖相迴路,時脈及資料回復,相位偵測器,頻率偵測器,連續速率, | zh_TW |
dc.subject.keyword | PLL,CDR,PD,FD,continuous-rate, | en |
dc.relation.page | 119 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2007-07-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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