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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | |
dc.contributor.author | Wang Hai-Ning | en |
dc.contributor.author | 汪海寧 | zh_TW |
dc.date.accessioned | 2021-06-08T05:56:39Z | - |
dc.date.copyright | 2008-02-01 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-01-28 | |
dc.identifier.citation | Reference
[1] O.M Clark ,“Transient voltage suppressor types and applications ”, IEEE Trans. Power Electron., vol. 5, pp. 20-26,Nov. 1986. [2] Bruce Hartwig,“What Is A Silicon Transient Voltage Suppressor And How Does It Work? ”, Vishay, TVS Catalog,, pp. 177, 2002. [3] Ya-Chin King, Bin Yu, Jeff Pohlman, and Chenming Hu, “Punchthrough Diode as the Transient Voltage Suppressor for Low-Voltage Electronics”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. II , pp. 2037-2040 NOVEMBER 1996 [4] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor,” Proc. International Semiconductor Conference, pp. 169-172 Sinaia, Romania (CAS'99) [5] Z. John Shen, Francine Y. Robb, Steve P. Robb, and David Briggs “Reducing Voltage Rating and Cost of Vehicle Power Systems With a New Transient Voltage Suppression Technology” IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 6, pp. 1652-1662 NOVEMBER 2003 [6] Ya-Chin King, Bin Yu, Jeff Pohlman, and Chenming Hu, “Punchthrough Transient Voltage Suppressor for Low-Voltage Electronics” IEEE ELECTRON DEVICE LE'ITERS, VOL. 16, NO. 7, pp. 303-305 JULY 1995 [7] David Flores, Xavier Jord`a, Salvador Hidalgo, Juan Fern´andez,Jos´e Rebollo, Jos´e Mill´an, I˜naki Sierra, and Imanol Mazarredo “An Optimized Bidirectional Lightning Surge Protection Semiconductor Device” IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 41, NO. 1, pp. 30-38 FEBRUARY 1999 [8] RICHARD B. FAIR, AND HAYDEN W. WIVELL ”Zener and Avalanche Breakdown in As-Implanted Low-Voltage Si n-p Junctions” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-23, NO. 5, pp. 512-518 MAY 1976 [8] J. B. Gunn, “Avlanche injection in semiconductors.” ,Proc. Phys. Soc., vol. B-69, pp. 781-790, 1956. [9] B. Jayant Baliga, Power Semiconductor Devices, Boston, MA: PWS, 1996. pp.82 [10] Sheng-Huei Dai, Hai-Ning Wang, Ming-Tai Chiang, Chrong-Jung Lin, and Ya-Chin King,“LEAKAGE SUPPRESSION OF LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR ”, IEEE 45th Annual International Reliability Physics Symposium, pp.592-593 Phoenix, 2007. [11] Hong Xiao, “Introduction to Semiconductor Manufacturing Technology”. Prentice Hall: 2001, pp.282 [12] “Ion Implantation Process Course Product Training Technical Reference Manual” Axcelis Technologies, Inc. 8201264 Rev. 2 March 2005 [13] S. M. Sze, Semiconductor Devices Physics and Technology, 2nd Edition”. JOHN WILEY: 2002, pp.163 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24805 | - |
dc.description.abstract | 摘要
突波抑制器廣泛的運用於保護電路使其不受過度電性應力的損害.過度電性應力可能來源有靜電放電,電感負載切換,或是雷擊.經由突波抑制器的保護,高伏突波將被“箝制”或經由PN接面之雪崩崩潰行為降低突波電壓到不致傷害元件的程度. 在電路中,突波抑制器於電路正常運作時是不工作的,在突波產生時才發揮其作用.因此其各項電氣特性.包括崩潰電壓,漏電,電容特性都應盡量不影響電路正常運作. 於本篇論文中,將對突波二極體進行研究.於製作流程中修改以降低重掺雜二極體於邊緣造成之漏電效應.修改之製程有(1)全面性離子植入(2)局部氧化製程以降低邊緣造成之漏電效應.實驗結果證明修改製程後元件可得到較好之漏電及崩潰電壓特性.我們也同時量測電容及突波承受能力.電容值會受到邊緣掺雜不均勻之影響但是主要影響還是來自於在主接面的不同離子植入濃度.而對於突波承受能力,主要影響也是來自於在主接面的不同離子植入濃度,不同離子植入濃度導致不同電容值及電阻值影響突波承受能力.高離子植入劑量將造成高電容/低電阻而可得到較高的突波承受能力.我們相信此一技術將可運用在保護元件上以得到較佳的保護能力. | zh_TW |
dc.description.abstract | Abstract
TVS (Transient Voltage Suppressor) is widely used to protect vulnerable circuits from electrical overstress such as that caused by electrostatic discharge, inductive load switching and induced lightning. Within the TVS, damaging voltage spikes are limited by clamping or avalanche action of a rugged silicon pn junction which reduces the amplitude of the transient to a nondestructive level. In a circuit, the TVS should be“invisible”until a transient appears. Electrical parameters such as breakdown voltage (V(BR)), standby leakage current (ID), and capacitance should have no effect on normal circuit performance. In this work, we proposed some simple modifications on the fabrication steps to effectively reduce the leakage current caused by the edge effect on the highly doped diode. The modifications include (1) blanket implantation and (2) LOCOS structure to reduce edge effect. Better leakage performance and breakdown voltage are achieved in the new proposed diodes. We also discussed the capacitance and surge performance in new structure diodes. The capacitance will be affected by edge uniformity but majorly impacted by the in main junction implantation dosage. And in surge performance, the major impact is also come from the main junction implantation dosage where causes different capacitance and resistance. High dosage will cause high capacitance / low resistance and get higher surge withstanding capability. We believed that this technique can be applied in protection device for better performance. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:56:39Z (GMT). No. of bitstreams: 0 Previous issue date: 2008 | en |
dc.description.tableofcontents | Contents
Abstract (Chinese) ...............................................................................I Abstract (English) ...............................................................................II Contents ................................................................................................III Table Captions ....................................................................................IV Figure Captions ...................................................................................V Chapter 1 Introduction....................……………….....................1 Chapter 2 Sample Preparation.....……………….....................12 Chapter 3 Measurement Result and Discussion….........…..30 3.1 Structures and Simulation Results.................………............31 3.2 Electrical Characteristics ..........................………………..32 3.2.1 BVR/IR Measurement ....................…………........32 3.2.2 Capacitance Measurement............................……...34 3.3 Surge Performance Measurement........................................37 Chapter 4 Conclusions ..................................................................54 References ............................................................................................56 | |
dc.language.iso | en | |
dc.title | 具不同邊界摻雜濃度突波抑制器二極體之模擬、製程與量測 | zh_TW |
dc.title | Simulation, Process and Measurement for TVS (Transient Voltage Suppressor) Diodes with Different Doping Concentrations in Edge | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭宇軒,林致廷 | |
dc.subject.keyword | 二極體, | zh_TW |
dc.subject.keyword | Diode, | en |
dc.relation.page | 57 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-01-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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