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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Ing-June Lu | en |
| dc.contributor.author | 盧盈君 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:56:01Z | - |
| dc.date.copyright | 2008-02-19 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-02-04 | |
| dc.identifier.citation | 1 D.A. Johns, and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons Inc., p.487, 1997.
2 A.N. Karanicolas, H. Lee, and K.L. Bacrania, “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC,” IEEE Journal of Solid-State Circuits, vol.28, no. 12, pp.1207-1215, December 1993. 3 E.G. Soenen, and R.L. Geiger, “An Architecture and An Algorithm for Fully Digital Correction of Monolithic Pipelined ADC’s,” IEEE Transactions on Circuits and Systems II, vol.42, no.3, pp.143-153, March 1995. 4 S. Chuang, and T.L. Sculley, “A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter,” IEEE Journal of Solid-State Circuits, vol.37, no.6, pp.674-683, June 2002. 5 Ｕ. Moon, and B. Song, “Background Digital Calibration Techniques for Pipelined ADC’s,” IEEE Transactions on Circuits and Systems II, vol.44, no.2, pp.102-109, February 1997. 6 J. Ming, and S.H. Lewis, “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration,” IEEE Journal of Solid-State Circuits, vol.36, no.10, pp.1489-1497, October 2001. 7 J. Li, and U. Moon, “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy,” IEEE Transactions on Circuits and Systems II, vol.50, no.9, pp.531-538, September 2003. 8 J.P. Keane, P.J. Hurst, and S.H. Lewis, “Background Interstage Gain Calibration Technique for Pipelined ADCs,” IEEE Transactions on Circuits and Systems I, vol.52, no.1, pp.32-43, January 2005. 9 J. Li, G. Ahn, D. Chang, and U. Moon, “A 0.9-V 12-mW 5-MSPS Algorithmic ADC With 77-dB SFDR,” IEEE Journal of Solid-State Circuits, vol.40, no.4, pp.960-969, April 2005. 10 H. Liu, Z. Lee, and J. Wu, “A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration,” IEEE Journal of Solid-State Circuits, vol.40, no.5, pp.1047-1055, May 2005. 11 J. Fan, C. Wang, and J. Wu, “A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs,” IEEE Transactions on Circuits and Systems I, vol.54, no.6, pp.1213-1223, June 2007. 12 Y. Chiu, C.W. Tsang, B. Nikolić, and P.R. Gray, “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters,” IEEE Transactions on Circuits and Systems I, vol.51, no.1, pp.38-46, January 2004. 13 S.H. Lewis, H.S. Fetterman, G.F. Gross Jr., R. Ramachandran, and T.R. Viswanathan, “A 10b 20Msample/s analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol.27, no.3, pp.351-358, March 1992. 14 D. Chang, J. Li, and U. Moon, “Radix-Based Digital Calibration Techniques for Multi-Stage Recycling Pipelined ADCs,” IEEE Transactions on Circuits and Systems I, vol.51, no.11, pp.2133-2138, November, 2004. 15 Ｓ. Haykin, Adaptive Filter Theory, 4th ed., Prentice Hall, pp.1-109, pp.203-278, 2002. 16 J. McNeill, M. Coln, and B. Larivee, “’Split ADC’ Architecture for Deterministic Digital Background Calibration of a 16-bit 1-MS/s ADC,” IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2437-2445, December 2005. 17 J. Li, U. Moon, J.A. McNeill, M. Coln, and B. Larivee, “Comments on ‘”Split ADC” Architecture for Deterministic Digital Background Calibration of a 16-bit 1MS/s ADC,’” IEEE Journal of Solid-State Circuits, vol.41, no.6, p.1481, June 2006. 18 J. McNeill, M. Coln, and B. Larivee, “A Split-ADC Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC,” in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.276-278, February 2005. 19 J. McNeill, et al, “Digital Background Calibration Algorithm for ‘Split ADC’ Architecture,” IEEE Transactions on Circuits and Systems II, submitted for publication. 20 賴玉玲，'淺談數值線性代數'，2007/12/17 http://www.math.sinica.edu.tw/math_media/d194/19405.pdf 21 C. Liu, “8-bit, High Conversion Rate Pipelined ADC With Improved Capacitors,” master thesis, National Taiwan University, June 2002. 22 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Inc., pp.410-423, 2000. 23 T. Cho, “Low-Power Low-Voltage Analog-to-Digital Conversion Techniques Using Pipelined Architecture,” Ph.D. Thesis, U.C. Berkeley, 1995. 24 P.E. Allen, and D.R. Holberg, CMOS Analog Circuit Design, 2nd Ed., Oxford University Press, pp.132-133, 2002. 25 A. Oppenheim, and R.W. Schafer, Discrete Time Signal Processing, 2nd Ed., Prentice Hall, pp.370-418, 1989. 26 C.E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchonous Clock Designs,” Sunburst Design, Inc. 27 IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000, pp.18-40. 28 M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no.8, pp.775-785, August 1986. 29 LM317 1.2V To 37V Voltage Regulator Data Sheet, ST® Microelectronics. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24748 | - |
| dc.description.abstract | 本文的目的為實做一具有背景數位校正功能的循環式類比數位轉換器，依循McNeil於2005年所發表分離式架構，建立整合類比數位轉換器與數位校正電路的實驗平台。所使用校正演算法，應用適應性濾波器原理，不需對前端類比電路注入額外校正訊號，對輸入訊號的影響最小。同時，分離式架構藉著數位校正的輔助，所佔面積只較傳統架構增加兩個比較器。
數位校正原理，假設相鄰的類比數位轉換器，其理想輸出可由兩者平均表示。將轉換器電路視為一特性未知的系統，即可設計一適應性濾波器，透過理想輸出與實際輸出的差值，利用最小均方法逼近此未知系統的特性參數，達到校正功能。 實驗晶片使用0.35微米互補式金氧半製程製作，操作電壓為3.3V，面積大小為1.5x1.5毫米平方。量測結果顯示，校正前分離式轉換器的解析度分別為45.70分貝與45.78分貝，相當於7.3有效位元與7.3有效位元；最大差分線性度分別為1.34最小位元與1.15最小位元，而最大積分線性度則為4.91最小位元與最小4.89位元（最小位元單位以十位元解析度計算）。數位電路在現場可程式邏輯閘陣列上實現，可操作之最高頻率為30.44百萬赫茲。整合後，系統的解析度由45.94分貝提升為54.43分貝，分別相當於7.33有效位元與8.74有效位元。校正前後的最大差分線性度分別為1.16最小位元與1.15最小位元，而最大積分線性度則由4.38最小位元改善至1.77最小位元。 | zh_TW |
| dc.description.abstract | This thesis realizes a cyclic analog-to-digital converter with background digital calibration according to the split-ADC architecture proposed by McNeill in 2005. The purpose is to establish an experimental platform on which the A/D converter and digital calibration circuit can be integrated. The calibration algorithm adopted does not require extra calibration signal to be injected in to the converter’s signal path, and therefore minimizes its effect on the input signal. Also, with the help of digital calibration, the overhead of implementing the split-ADC architecture is reduced. It only increases two extra comparators compared with the traditional architecture.
The underlying calibration principle assumes the average of two adjacent A/D converters as the ideal conversion result. The converter then may be taken as an unknown system whose characteristics can be probed with an adaptive filter. Using the assumed ideal conversion results and the real conversion output, one may apply the least-mean-square method. In this way, the actual parameters of the individual ADCs is found, completing the digital calibration procedure. The chip has been fabricated using 0.35 um CMOS process, occupying area of 1.5x1.5 mm2. Measurement results show that the split-ADCs exhibit resolution of 45.70 dB and 45.78 dB, equivalent to ENOB of 7.3 bits and 7.3 bits, respectively. The maximum DNL of the converters are 1.34 LSB and 1.15 LSB, and the maximum INL are 4.91 LSB and 4.89 LSB, respectively. (LSB unit is calculated assuming 10-bit resolution) Digital calibration circuit is realized on FPGA, with maximum achievable operating frequency of 30.44 MHz. After integration, the system improves the resolution from 45.94 dB to 54.43 dB, which equivalently improves ENOB from 7.33 to 8.74. Maximum DNL are 1.16 LSB and 1.15 LSB before and after calibration, respectively, and maximum INL drops from 4.38 LSB to 1.77 LSB. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:56:01Z (GMT). No. of bitstreams: 1 ntu-97-J94921019-1.pdf: 24592572 bytes, checksum: 21ed2f013d21eca3f7a4afb1d1edb5ff (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 第1章 緒論 1
1.1 緒論與動機 1 1.2 數位校正的歷史 2 1.3 背景數位校正技術與文獻探討 2 1.4 論文內容架構 3 第2章 背景數位校正技術的工作原理 4 2.1 循環式類比數位轉換器與基底校正原理 4 2.1.1 循環式類比數位轉換器的工作原理 4 2.1.2 循環式類比數位轉換器的誤差來源 7 2.1.2.1 運算放大器的有限增益 7 2.1.2.2 電容不匹配 8 2.1.2.3 比較器的位準偏移 9 2.1.3 基底數位校正技術 10 2.2 分離式類比數位轉換器架構與適應性校正技術 11 2.2.1 適應性濾波器原理 11 2.2.2 分離式架構與理想輸出的表示法 14 2.2.3 分離式架構對電路特性的影響 14 2.2.4 分離式類比數位轉換器的數位校正演算法簡介 15 2.3 數位校正演算法的數學演繹 17 2.3.1 系統偏移及比例誤差的存在 17 2.3.2 可容忍系統偏移及比例誤差的數學模式 18 2.3.3 矩陣求解與適應性濾波器原理的應用 20 2.4 系統穩定度與路徑選擇問題 22 2.5 系統行為模擬 24 2.5.1 行為模型的建立 24 2.5.1.1 循環式類比數位轉換器 24 2.5.1.2 數位校正電路 25 2.5.2 模擬結果 28 第3章 前端循環式類比數位轉換器的電路設計 30 3.1 系統架構與規格 30 3.1.1 系統架構 30 3.1.2 設計規格 31 3.1.2.1 基本規格 31 3.1.2.2 循環次數 31 3.1.2.3 運放大器規格 32 3.1.2.4 比較器參考電壓 32 3.2 細部電路設計 33 3.2.1 次級類比數位轉換器 33 3.2.1.1 取樣開關 35 3.2.1.2 取樣電容 36 3.2.1.3 運算放大器 38 3.2.1.4 取樣電路 40 3.2.1.5 倍乘電路 41 3.2.1.6 動態比較器與前置放大器 42 3.2.1.7 路徑選擇邏輯電路 44 3.2.2 雙相非重疊時脈產生器 46 3.2.3 輸入控制訊號產生器 47 3.2.4 參考電壓產生電路 48 3.2.5 輸出介面電路 50 3.3 模擬結果與布局考量 51 3.3.1 佈局前模擬結果 51 3.3.2 佈局考量與佈局後模擬結果 52 第4章 數位校正電路的設計 54 4.1 設計考量 54 4.1.1 演算法的簡化 54 4.1.2 有限小數表示法 54 4.2 系統架構 56 4.3 功能區塊電路說明 57 4.3.1 數位碼及增益誤差模產生模組（xsdka、xsdkb） 57 4.3.2 平均及輸出差模組（outgen） 58 4.3.3 延遲模組（sdgen） 59 4.3.4 更新模組（eggen） 60 4.3.5 控制器電路 61 4.4 驗證模組設計與模擬方法 64 4.4.1 測試模型和測試平台的設計 64 4.4.2 與行為模型整合驗證 65 第5章 系統整合與類比數位共同模擬 67 5.1 共同模擬的方法與流程 67 5.2 同部問題與數位介面電路 68 5.2.1 同步問題 68 5.2.2 同步介面電路設計 69 5.2.3 除頻電路 70 5.3 模擬驗證結果 71 第6章 晶片系統量測 72 6.1 測試流程與方法 72 6.1.1 測試流程 72 6.1.2 測試方法 72 6.2 類比晶片的量測 72 6.2.1 量測裝置 72 6.2.2 印刷電路板設計 74 6.2.3 量測結果 76 6.3 數位電路的原型驗證 78 6.3.1 驗證方法 78 6.3.2 數位電路測試腳位設定 80 6.3.3 驗證結果 82 6.3.3.1 電路合成結果摘要 82 6.3.3.2 邏輯分析儀驗證結果 84 6.4 系統整合 85 6.4.1 系統整合 85 6.4.2 整合量測結果 85 6.4.3 量測結果摘要 89 第7章 討論與結論 90 7.1 量測結果比較 90 7.2 討論 91 7.3 未來發展方向 92 7.4 結論 92 附錄A 採用另一種佈局方式的晶片量測結果 94 參考文獻 100 | |
| dc.language.iso | zh-TW | |
| dc.title | 具背景數位校正功能的分離式架構循環式類比數位轉換器的實現 | zh_TW |
| dc.title | Realization of a Cyclic ADC with Split Architecture and Digital Background Calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien (Eric) | |
| dc.subject.keyword | 分離式架構,循環式類比數位轉換器,背景數位校正,適應性濾波器, | zh_TW |
| dc.subject.keyword | split architecture,cyclic analog-to-digital converters,background digital calibration,adaptive filter, | en |
| dc.relation.page | 103 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-02-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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