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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | Chi-An Chen | en |
| dc.contributor.author | 陳麒安 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:34:05Z | - |
| dc.date.copyright | 2005-02-17 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-02-01 | |
| dc.identifier.citation | [1] Behead Razavi,”RF Microelectronics,” Prentice Hall 1998
[2] 賈志靜 ”數位類比通信系統,”全華科技圖書股份有限公司1999 [3] WEN SHING: www.wenshing.com.tw [4] Yu-Tso Lin,”The Design and Application of Low Noise Amplifier and Frequency Divider for Radio Communication Systems,” National Taiwan University MS. Thesis, June 2003. [5] Webster,”Medical Instrumentation Application and Design,” WILEY 1998 [6] Chen-Ming Hsu,”Implementation of microwave biotelemetry chip,” National Cheng Kung University MS. Thesis, June 2003 [7] Jen-Chang Su,”The Study and Implementation of A Light and Portable Wireless ECG Device,” National Cheng Kung University MS. Thesis, June 2002 [8] Min-Xuan Chang,”12-Lead Image Format ECG System Improvement and Clinical Database Development,” National Yang-Ming University MS. Thesis, July 2003 [9]涂清源,”Development of Home-care System Using RF Transceiver and Internet,” Chun Yuan Christian University MS. Thesis, July 2002 [10] H. Murakami, K. Shimizu, K. Yamamoto, T. Mikami, N. Hoshimiya, and K. Kondo,” Telemedicine Using Mobile Satellite Communication,” IEEE Transactions on Biomedical Engineering, Vol. 41, No.5, May 1994 [11] J.Bai, Y. Zhang, D. Shen, L. Wen, C. Ding, Z. Cui, F. Tian, B. Yu, B. Dai, J. Zhang,”A Portable ECG and Blood Pressure Telemonitoring System,” IEEE Engineering in Medicine and Biology, July/August 1999 [12] B. Woodward, R. S. H. Istepanian, and C. I. Richards,” Design of a Telemedicine System Using a Mobile Telephone,” IEEE Transactions on Information Technology in Biomedicine, Vol.5, No.1, March 2001 [13] K. Shimizu,” Telemedicine by Mobile Communication,” IEEE Engineering in Medicine and Biology, July/August 1999 [14] A. I. Hernandez, F. Mora, G. Villegas, G. Passariello, and G. Carrault,” Real-Time ECG Transmission via Internet for Nonclinical Application,” IEEE Transactions on Information Technology in Biomedicine, Vol.5, No3, September 2001 [15] 胡茂林,”8088微處理機原理與應用實作,” 全華科技圖書股份有限公司, 1996 [16] 蕭子健,林俊宏,彭宇豪,”LabVIEW 硬体介面篇,”高立圖書股份有限公司, 2002 [17] 范逸之 陳立元 孫德萱 程正孚,”Visual Basic 與串並列通訊控制實務,”文魁資訊股份有限公司, 2002 References [18] Thomas B. Cho, David W. Cline, Cormac S.G. Conroy, and Paul R. Gray,” Design Considerations for High-Speed Low-Power Low-Voltage COMS Analog-to-Digital Converters,” UC Berkeley [19] G. Chien,” High-Speed, Low-Power, Low-Voltage, Pipelined Analog-to-Digital Converter,” UC Berkeley MS. Thesis, 1996 [20] David WIllian Cline,” Noise, Speed, and Power Trade-offs in Pipelined Analog to Digital Converters,” UC Berkeley PhD. Thesis, 1995. [21] K. Y. Kim, N. Kusayanagi, A. A. Abidi,” A 10 bit, 100MHz A/D Converter in 1-um COMS,” UC Berkeley June 1996. [22] 鄭光偉,”A 1.0-V,10-Bit CMOS Pipeline Analog-to-Digital Converter,” National Taiwan University MS. Thesis, June 2002. [23] Hsien-Chun Liu,”Design of a 100MHz 10-Bit Analog to Digital Converter with Pipeline Architecture,” National Chiao-Tung University MS. Thesis, June 2003. [24] Behead Razavi,” Principles of Data Conversion system Design,” IEEE PRESS, 1995. [25] David A. Johns, Ken Martin,” Analog Integrated Circuit Design,” John Wiley& Sons, Inc. 1997. [26] Mikael Gustavsson, J. Jacob Wikner, and Nianxiong Nick Tan,” COMS Data Converters for Communications,” Kluwer Academic Publishers, 2000. [27] Alfi Moscovici,”High Speed A/D Converters Understanding Data Converters Through SPICR,”2001. [28] R.Jacob Baker, Harry W. Li, David E. Boyce,” CMOS Circuit Design, Layout, and Simulation,” IEEE PRESS, 1998. [29] C. W. Mangelsdorf,” A 400-MHz Input Flash Converter with Error Correction,” IEEE J. Solid-State Circuits, Feb.1990, pp. 184-191 [30] J. Doernberg, P. R. Gray, David A. Hodges,” A 10-bit 5-Msample/s CMOS Two-Step Flash ADC,” IEEE J. Solid-State Circuits, April 1989, pp. 241-249. [31] Myung, Jun Choe, Bang. Sup Song, Kantial Bacrania,”An 8-b 100-MSample/s CMOS Pipelined Folding ADC,” IEEE J. Solid-State Circuits, Feb 2001, pp. 184-194. [32] Ardie G. W. Venes, Rudy J. van de Plassche,” An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” IEEE J. Solid-State Circuits, Dec. 1996, pp. 1846-1853. [33] Yong-Lin Huang,”A High-Speed Folding and Interpolating A/D Converter with Improved Offset Averaging Techniques,”National Cheng-Kung University MS. Thesis June 2002 [34] Thomas Byunghak Cho, P. R. Gray,” A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,” IEEE J. Solid-State Circuits, March 1995, pp. 166-172. [35] S. H. Lewis, P. R. Gray,”A Pipeline 5-Msamples/s 9-bit Analog-to-Digital References Converter,” IEEE J. Solid-State Circuits, March 1992, pp. 351-358. [36] Andrew M. Abo, P. R. Gray,” A 1.5V, 10-Bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, May 1999, pp. 599-606. [37] James L. McCrery, P. R. Gray,”All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I,” IEEE J. Solid-State Circuits, Dec. 1975, pp. 371-378. [38] Bahram Fotouhi, David A. Hodges,” High-Resolution A/D Conversion in MOS/LSI,” IEEE J. Solid-State Circuits, Dec. 1979, pp. 920-926. [39] M. J. McNutt, S. LeMarquis, J. L. Dunkley,” Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. Solid-State Circuits, May 1994, pp. 611-616. [40] DiaaEldin Sayed, Mohamed Dessouky,”Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” IEEE 2002 [41] Charles H. Roth, Jr.”Fundamentals of Logic Design,”PWS Publishing Company [42] Neil H. E. Weste, Kaman Eshraghian,”Principles of CMOS VLSI Design,” Addision-Wesley Publishing Company [43] G. M. Yin, F. Op’t Ehnde, W. Sansen,” A High-Speed CMOS Comparator with 8-b Resolution,” IEEE J. Solid-State Circuits, Feb. 1992, pp. 208-211. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24630 | - |
| dc.description.abstract | 本論文的目的在於無線生醫監測系統之人体訊號監測器的積体電路設計，用以降低其功率損秏及其体積，進一步的使人体訊號監測器能夠使用更久更輕便，在本論文中主要在於實現適用於無線生醫監測系統之類比數位轉換器的積体電路部分，其它的部分例如射系統以及訊號放大器則使用外部模組，在實驗整個系統的穩定性及可行性之後在未來才將其它部分一起整合在單一顆積体電路中；在本論的內容中包含了基本的無線系統、無線生醫系統、心電圖的電路及其訊號、各種常見的類比數位轉換器架構及其基本特性、混合式類比數位轉換器的實現、及混合式類比、數位轉換器和生醫系統的量測及實驗，文章內容主要分成三個部分：
第一部分，了解常見之無線傳輸架構其傳輸方式及傳輸速率，在目前常用的無線系統主要為 802.11、Bluetooth、ASK、FSK，這些無線的架構其傳輸速率皆大於4.8KBPS所以皆可以用來傳輸心電圖系統因為心電圖的頻寬大約需100Hz，而為了低功率及小体積所以先選用架構較簡單的ASK及FSK，在對訊號和傳輸系統的分析和了解有了初步的了解之後，便可以進一步的依照所需要的規格設計類比數位轉換器的基本功能方塊，以做為後續電路設計的依據，其規格主要為 7位元的類比數位轉換器並操作在5.5MHz 而類比數位轉換器的並列輸出經由一個多工器(MUX)轉為串列輸，而多工器的輸(MUX)出主要符合廣用收發器(UART)的格式。 第二部分，了解各式類比數位轉換器的原理及其優缺點，由於並非所有類比數位轉換器結構可以適用於無線生醫監測系統，最後選擇出來的類比數位轉換器的結構為電容電阻混合式有效近似類比數位轉換器，並以台灣積体電路公司(TSMC)所提供的CMOS 0.35微米 2P4M製程來進行設計及模擬。 第三部分，對於所設計的積体電路進行基本的量測，經由測量之後類比數位轉換器其操作在1.5KHz1.8伏特的輸入時，其微分型非線性誤差為0.6個最小單位而積分型非線性誤差為1.3個最小單位，有效位元數為6位元；多工器在經由測試之後其工能正常，之後把此顆積体電路整合成一個監測電路之後亦可傳輸溫度及心電圖。 | zh_TW |
| dc.description.abstract | The purpose of this thesis is for the IC design of the wireless biotelemetry system in order to reduce the power consumption and volume. Moreover, the integrated circuit causes the wireless biotelemetry system to use longer and more convenient than hybrid system. In the thesis, the IC of ADC for wireless biotelemetry system is implemented firstly. The other part of the system is used by the module. After the stability and feasibility of the system is experimented, the RF system and amplifier will be integrated in the same chip. The concepts of this thesis include the basic RF systems, the wireless biotelemetry systems, and ECG signal; moreover, this thesis also introduces the basic architectures and properties of the ADC, the implement of Hybrid SAR ADC, and the experiments of the wireless biotelemetry system which includes the Hybrid SAR ADC. This thesis is divided into three parts:
The fist part is used to understand the common architectures and the transmission rate of wireless system which is 802.11, Bluetooth, ASK, and FSK usually. The transmission rate of these wireless architectures is enough for the ECG system because the bandwidth of ECG signal is about 100Hz. In order to reduce the power consumption and volume, the ASK and FSK are chosen firstly. The function blocks are implemented for the circuit design of ADC after the understanding of transmission system. The specs of function blocks is 7bit ADC which is operated at 5.5MHz, and the ADC parallel outputs is transferred into series output which follows the UART interface by a MUX. The second part is used to understand the principles and advantages of architectures of ADC because not all the architectures are suitable to be implemented in the wireless biotelemetry systems. The Hybrid SAR ADC is chosen for the application and is designed by the TSMC CMOS 0.35um 2P4M process. In the third part, the IC is measured and the input is 1.8V 1.5 KHz. The INL is 0.6LSB, DNL is 1.3LSB, and ENOB is 6bit. The MUX works rightly, and the experiments of the temperature and ECG are presented. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:34:05Z (GMT). No. of bitstreams: 1 ntu-94-R91943028-1.pdf: 2696901 bytes, checksum: e19c16f4272f55f491a7f7e3709a0cb4 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Contents
Chapter 1 Introduction ………………………………………………………………… 1 1.1 Motivation and Goal ………………………………………………………………. 1 1.2 Thesis Organization …………………...…………………………………………… 2 Chapter 2 The Wireless Biotelemetry System ………………………………………… 3 2.1 Introduction ……………………………………………………………………….. 3 2.2 Basic Concepts of Wireless Systems …………………………………………….. 3 2.3 Basic Concepts of Wireless Biotelemetry Systems ………………………………. 6 2.3.1 Bio-Medical Signals …………………………………………………………. 6 2.3.2 The Standard Lead Systems of ECG Signal Detection ………………………. 8 2.3.3 The Distortions of ECG Signal …………………………………………...… 10 2.3.4 Previous Developments of Wireless Biotelemetry Systems ……………...… 11 2.3.5 Computer Communication Protocol …………………………………...…… 13 2.4 The Design of Wireless Biotelemetry System …………………………………..... 14 Chapter 3 The Basic Concepts of ADC ………………………………………………. 18 3.1 Introduction ………………………………………………………………………. 18 3.2 High Speed ADC …………………………………………………………………. 19 3.2.1 High Speed ADC: Fully Flash ADC ……………………………………….. 19 3.2.2 High Speed ADC: Two Step Flash ADC …………………………………… 21 3.2.3 High Speed ADC: Pipeline ADC …………………………………………… 22 3.3 Medium Speed ADC: Successive-Approximation ADC …………………………. 23 3.3.1 SAR ADC Function Blocks ………………………………………………… 24 3.3.2 SAR ADC Binary Search Algorithm ………………………………………. 25 3.3.3 Binary-Weighted DAC Architecture ………………………………………. 27 3.3.3.1 R-2R Architecture ………………………………………………… 27 3.3.3.2 Charge Redistribution Architecture ………………………………. 28 3.3.3.3 Current Mode Architecture ……………………………………….. 28 3.4 Low Speed ADC: Oversampled ADC …………………………………….…….... 29 3.5 ADC Performance Metrics ………………………………………………………. 30 3.5.1 Resolution ………………………………………………………………….. 30 3.5.2 Signal to Noise Ratio …………………………………………………….… 30 3.5.3 Signal to Noise + Distortion Ratio ………………………………….…….... 31 3.5.4 Dynamic Range …………………………………………………………..… 31 3.5.5 Nonlinearity ………………………………………………………………… 32 Chapter 4 The Implementation of Hybrid SAR ADC with UART Interface …………. 33 4.1 Introduction …………………………………………………………………….… 33 4.2 The Operation of Hybrid SAR ADC …………………………………………...… 33 4.3 Circuit Design of Hybrid SAR ADC ……………………………………………... 39 4.3.1 Cap Array and Resister Array ……………………………….……………… 39 4.3.1.1 Factor of Accuracy ……………………………………..……………. 39 4.3.1.2 Factor of Conversion Rate ……………………………….………….. 45 4.3.2 Logic Controller ……………………………………………………………. 48 4.3.3 Comparator …………………………………………………………………. 52 4.3.4 Simulation Result of Hybrid SAR ADC …………………………………… 57 4.4 The Operation of MUX …………………………………………………………... 58 4.5 The Design of MUX ……………………………………………………………… 59 4.6 Simulation Result of MUX ……………………………………………………….. 65 4.7 Layout and Floor Plan of Hybrid SAR ADC with UART Interface ……………… 65 Chapter 5 The Measurements and Experiments of Hybrid SAR ADC with UART Interface ……………………………………………………………………………… 66 5.1 Introduction ………………………………………………………………………. 66 5.2 Test Setup ………………………………………………………………………… 66 5.3 Measurement Results ……………………………………………………………. 69 5.3.1 Hybrid SAR ADC Measurement Results ………………………………….. 69 5.3.1.1 Code density, INL, DNL Test ………………………………………. 69 5.3.1.2 SNDR, ENOB Test …………………………………………………. 70 5.3.2 Measurement Result Summary …………………………………………...... 72 5.3.3 MUX Measurement Result …………………………………………………. 72 5.4 The Experiment of Wireless Biotelemetry System ……………………………...... 73 5.4.1 The Wireless Temperature Biotelemetry Experiment ………………………. 73 5.5 The ECG Biotelemetry Experiment ………………………………………………. 75 Chapter 6 Conclusions ……………………………………………………………….. 76 References ……………………………………………………………………………. 77 Appendix ……………………………………………………………………………... 80 List of Figures Fig 2.1 Digital communication system ………………………………………………… 4 Fig 2.2 ASK modulation ……………………………………………………………….. 4 Fig 2.3 FSK modulation ……………………………………………………………….. 5 Fig 2.4 PSK modulation ……………………………………………………………….. 5 Fig 2.5 QPSK Modulation ..…………………………………………………………… 5 Fig 2.6 ECG signal …………………………………………………………………….. 7 Fig 2.7 Dipole moment/Cardiac vector of ECG signal ……………………………...… 8 Fig 2.8 Front plane lead system ………………………………………………….…….. 8 Fig 2.9 Eindhoven`s triangle ……………………………………………………...…… 9 Fig 2.10 Circuits of Eindhoven`s triangle …………………………………………….. 9 Fig 2.11 Wilson`s central terminal ……………………………………………………. 10 Fig 2.12 Unipolar augmented limb leads ………………………………………...…… 10 Fig 2.13 Unipolar precordial leads ……..…………..……………………………….... 10 Fig 2.14 Equivalent circuit of electrode ……………………………………………… 11 Fig 2.15 Noise of ECG signal ……..……..…………………………………………… 11 Fig 2.16 The analog wireless bio system of Koichi Shimizu ………………………… 12 Fig 2.17 The digital wireless bio system of Koichi Shimizu …………………………. 12 Fig 2.18 The system development of Alfredo I. Hernandez ………………………….. 12 Fig 2.19 The system blocks of Alfredo I. Hernandez ………………………………… 13 Fig 2.20 UART interface format …………..……………………………………….… 14 Fig 2.21 The function blocks of wireless biotelemetry system ………………………. 15 Fig 2.22 The function blocks of wireless biotelemetry system with controller……….. 15 Fig 2.23 The architecture of ADC with UART interface …………………………….. 16 Fig 2.24 The Trigger Signal Controls the Repeat Times of the ADC output …………. 16 Fig 3.1 The properties of ADC architectures ……………………………………….... 19 Fig 3.2 Fully Flash Architecture ……………………………………………………… 20 Fig 3.3 Two step ADC ……………………………………………………………...… 21 Fig 3.4 Folding ADC ……………………………………………………………….… 21 Fig 3.5 Pipeline ADC …………………………………………………………………. 23 Fig 3.6 The Function Blocks of SAR ADC ……………………………………...…… 24 Fig 3.7 An example of successive approximation ……………………………………. 26 Fig 3.8 Successive approximation flow chart ………………………………………… 26 Fig 3.9 R-2R resister ladder architecture …………………………………………… 27 Fig 3.10 The DAC architecture of R-2R resister ladder ……………………………. 27 Fig 3.11 The DAC architecture of charge redistribution ……………………………... 28 Fig 3.12 Current Steering DAC architecture …………………………………………. 29 Fig 3.13 Oversampled ADC architecture …………………..………………………… 29 Fig 3.14 Ideal Transfer Curve of ADC ……………………………………………….. 30 Fig 3.15 Quantization error distribution ……………………………………………… 31 Fig 3.16 Dynamic Range …………………………………………………………… 32 Fig 3.17 INL and DNL ……………………………………………………………… 32 Fig 4.1 Hybrid SAR ADC system architecture ………………………………………. 33 Fig 4.2 The detailed architecture of ADC clock system and ADC registers …………. 34 Fig 4.3 The time sequence of logic controller and binary-weight voltage of node Vx at Vin=0 …………………………………………………………………………………. 35 Fig 4.4 The sample and hold mode of ADC ………………………………………..… 36 Fig 4.5 16CS cycle ……………………………………………………………………. 36 Fig 4.6 The register stores the comparison result and controls the 16C switch …….... 37 Fig 4.7 RS1 cycle …………………………………………………………………..… 38 Fig 4.8 RS0 cycle …………………………………………………………………….. 38 Fig 4.9 Binary weighted cap ………………………………………………………….. 40 Fig 4.10 SAR ADC accuracy simulation system ……………………………….......… 40 Fig 4.11 Simulation result of C=400fF …………………………………………..…… 41 Fig 4.12 Layout of Common Centroid Cap Array ……………………………………. 43 Fig 4.13 Common Centroid Cap Array Simulation System ………………………..… 43 Fig 4.14 RC of sampling mode ……………………………………………………….. 45 Fig 4.15 The RC time constant of cap array redistribution cycle …………………….. 46 Fig 4.16 The RC time constant of cap array and resister array redistribution cycle .… 47 Fig 4.17 Logic Controller Logic Architecture ………………..……………………… 48 Fig 4.18 Architecture of register with reset …………………………………………... 50 Fig 4.19 Simulation of logic controller time sequence ………………………………. 51 Fig 4.20 The binary-weight voltage of binary search at Vx ………………………….. 52 Fig 4.21 The basic function block of comparator …………………………………….. 52 Fig 4.22 The architecture of latch in regeneration mode …………………………… 53 Fig 4.23 The regeneration phase ……………………………………………………. 53 Fig 4.24 Architecture of comparator ………………………………………………….. 54 Fig 4.25 Comparator accuracy ……………………………………………………...… 55 Fig 4.26 Comparator conversion time ……………………………………………….. 56 Fig 4.27 Architecture of nonoverlap clock generator ………..………………………. 56 Fig 4.28 Simulation of nonverlap clock generator …………..………………………. 56 Fig 4.29 INL and DNL of ramp 0V~1.107V ……………………………………….. 57 Fig 4.30 INL of ramp 1.107V~2V ………………………………………………….. 57 Fig 4.31 DNL of ramp 1.107V~2V …………………………………………………... 58 Fig 4.32 SNFR test of Hybrid SAR ADC …………………………………………… 58 Fig 4.33 The architecture of MUX ………………………………………………….. 59 Fig 4.34 The time sequence of MUX ……………………………………………….. 59 Fig 4.35 The architecture of MUX main block ……………………………………… 60 Fig 4.36 The total circuit of MUX ……………………………………………………. 64 Fig 4.37 Simulation of MUX …………………………………………………………. 65 Fig 4.38 Layout and floor plan of the hybrid SAR ADC with UART interface ……… 65 Fig 5.1 Test setup …………………………………………………………………… 66 Fig 5.2 PCB of regulators and IC ………….……………………………………….. 67 Fig 5.3 Total testing system ………………………………………………………… 68 Fig 5.4 The computer logic analyzer and computer function generator ……………… 68 Fig 5.5 Regulator …………………………………………………………………….. 68 Fig 5.6 Die Photo of IC …………………………………………………………….. 68 Fig 5.7 The data was received form computer Logic Analyzer in picture format ……. 69 Fig 5.8 The logic analyzer output(ramp with fit curve) is synthesized by Matlab …. 69 Fig 5.9 INL …………………………………………………………………………... 69 Fig 5.10 DNL …………………………………………………………………………. 70 Fig 5.11 The data was received form computer logic analyzer in picture form ……… 70 Fig 5.12 The logic analyzer output(5KHz) is synthesized by Matlab ……………… 70 Fig 5.13 FFT of 5KHz input sinusoid …………….………………………………… 71 Fig 5.14 Measurement Result of SNDR and ENOB …………………………………. 71 Fig 5.15 Measurement result of MUX ……………………………………………..… 72 Fig 5.16 The temperature monitor system ……………………………………………. 73 Fig 5.17 Controller …………………………………………………………………… 73 Fig 5.18 Sensor ……………………………………………………………………….. 73 Fig 5.19 Sensor circuit …..…………………………………………………………… 74 Fig 5.20 Clock generator …..………………………………………………………… 74 Fig 5.21 The experiment of temperature biotelemetry ……………………………….. 74 Fig 5.22 The LabVIEW experiment ………………………………………………….. 75 Fig appendix1 FM transmitter ……………………………………………………….. 80 Fig appendix2 ECG signal ……………………………………………………………. 81 List of Tables Table 2.1 RF systems ………………………………………………………………..… 6 Table 2.2 The typical nature signal of body …………………………………………… 7 Table 2.3 UART interface …………………………………………………………..… 13 Table 3.1 The list of ADC architectures ……………………………………………... 18 Table 3.2 Thermometer Code of 3Bit Fully Flash ADC ……………………………… 20 Table 3.3 Effective bits VS. residue amplifier gain and number of comparator in 10 bit ADC ………………………………………………………………………………….. 23 Table 4.1 The simulations of process variation ……………………………………… 42 Table 4.2 Simulation of common centroid cap array ………………………………… 44 Table 4.3 Simulation of common centroid cap array with resister array …………….. 44 Table 4.4 Design value of cap array and resister array ………………………………. 47 Table 4.5 Logic controller Gray Code and function ………………………………….. 49 Table 4.6 True value table of Gray Code …………………………………………….. 49 Table 4.7 The function generation logic of logic controller ………………………….. 50 Table 4.8 Summary of simulation results …………………………………………….. 58 Table 4.9 The Gray Code and Functions of MUX ……………………………………. 61 Table 4.10 True value table of MUX Gray Code ……………………………………... 62 Table 4.11 Function of MUX …………………………………………………………. 63 Table 4.12 True value table of function of high ………………………………………. 64 Table 5.1 Measurement result summary ……………………………………………… 72 | |
| dc.language.iso | en | |
| dc.title | 用於無線生醫監測系統之類比數位轉換器 | zh_TW |
| dc.title | ADC for Wireless Biotelemetry System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孟慶宗,孫台平,蘇炎坤,詹益仁 | |
| dc.subject.keyword | 無線生醫監測系統,類比數位轉換器, | zh_TW |
| dc.subject.keyword | Wireless Biotelemetry System,ADC, | en |
| dc.relation.page | 81 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2005-02-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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