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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇 | |
| dc.contributor.author | Chih-Hsiu Lin | en |
| dc.contributor.author | 林志修 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:31:40Z | - |
| dc.date.copyright | 2005-07-14 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-06-27 | |
| dc.identifier.citation | [1] Amendment: Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10Gb/s Operation, IEEE Standard 802.3ae-2002.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24576 | - |
| dc.description.abstract | 可適應性等化器(adaptive equalizers)在近代的數位通訊系統收器中扮演著關鍵的模組，因為等化器設計的好壞經常決定系統能傳輸的最大速率及品質，而且它所秏的計算量占了系統的總計算量中相當大的一部分。所以不論在研究上和實際應用上，等化器都佔有相當的重要性。目前研究重心仍為設計更快的通訊系統和更高密度的儲存裝置，然而隨著傳輸速率的增加和儲存裝置密度的提高，通道的失真產生的碼際干擾(intersymbol interference, ISI)對傳輸訊號造成的失真越來越嚴重。因此，設計一個高抗雜訊、高抗失真且能在高速下操作的等化器將是非常重要且必需的研究議題。
傳統的迴饋決策等化器(decision feedback equalizer)能有效的抑制碼際干擾，卻會因錯誤的決策而造成錯誤蔓延(error propagation)，進而造成系統的錯誤率提高和連續錯誤長度(burst error length)增加等效應。在本論文的第一部份，我們提出多層軟性迴饋決策等化器(soft threshold-based multi-layer decision feedback equalizer, STM-DFE)演算法來抑制錯誤蔓延。模擬顯示多層軟性迴饋決策等化器能有效降低錯誤率和連續錯誤長度。在磁帶儲存通道上模擬，多層軟性迴饋決策等化器的性能甚至超過完美迴饋決策等化器(假設迴饋決策皆為正確) 。 此外超大型積體電路的實作上，多層軟性迴饋決策等化器比傳統迴饋決策等化器增加的額外硬體相當少。本論文的第二部份探討等化器在高速的應用上，我們提出的兩階段預算法(two-stage precomputation)能有效的降低多層軟性迴饋決策等化器在高速應用上的硬體成本。同時我們提出了其相對應的可適應性演算法來降低硬體成本和能量消秏。在10GBase-LX4光纖通訊系統的應用上，多層軟性迴饋決策等化器更將類比數位轉換器(analog-to-digital converter)所需的精確度從8位元降至6位元。利用此演算法，我們可以減輕設計類比數位轉換器困難度、複雜度及降低所需的硬體成本。 | zh_TW |
| dc.description.abstract | An adaptive equalizer plays a key role at the receiver in modern digital transmission systems. The design of this equalizer is important since it determines the transmission quality attainable. Also, the equalizer occupies a high portion of the computational complexity in implementing the demodulator. Theses properties have made it the focus of much analytical and practical design. Recently, many researches of interest in communication systems are to increase transmission rate and recording density. However, with the increase of transmission rate and recording density, the signals propagating the channel suffer from serious channel distortion, which causes intersymbol interference (ISI). Hence, to design a robust and high-speed equalizer becomes important and necessary.
A decision feedback equalizer (DFE) is an efficient scheme to suppress this ISI. However, most cost-effective DFE implementations suffer from the phenomenon of error propagation, which degrades system performance in the sense of bit error rate (BER) or signal-to-noise ratio (SNR). In this thesis, we propose a soft-threshold-based multi-layer DFE (STM-DFE) algorithm to suppress the error propagation. Simulation results show that the proposed STM-Algorithm can efficiently reduce the BER and burst error length (BEL). When being applied to a practical Lorentzian channel and channels of different eigenvalue spread, the STM algorithm even outperforms the ideal DFE (IDFE) system (in an IDFE, symbols are assumed to be correctly fed back without propagation errors). In VLSI implementations of the STM-DFE, the hardware overhead is negligible compared with a conventional DFE. The direct implementation can be applied to low-speed application such as magnetic data storage systems. In addition, for high-speed applications, we propose a two-stage precomputation scheme to lower the hardware overhead. A new adaptive algorithm to update for a DFE with precomputation scheme is also proposed so that both hardware complexity and power consumption can be saved. Finally, we consider the application of the STM-DFE to 10GBase-LX4 systems. With the help of the STM-DFE, we can perform effective EQ, and the required bit number of ADC can be reduced from 8 to 6. That is, STM-DFE can help to ease the ADC precision requirement, and help to save the silicon cost in implementing the receiver ICs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:31:40Z (GMT). No. of bitstreams: 1 ntu-94-F89921096-1.pdf: 8312090 bytes, checksum: d8a8b87e5988826a610fd05743fb44cc (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Abstract - 1 -
Lists of Figures - 7 - List of Tables - 12 - Chapter 1 Introduction - 13 - 1.1 Research Motivation - 15 - 1.2 Research Contributions - 19 - 1.3 Thesis Organization - 22 - Chapter 2 Implementation Impairments of Existing Decision Feedback Equalizers - 24 - 2.1 Review of Equalizer Designs - 24 - 2.2 Error Propagation in DFE - 28 - Chapter 3 Soft Threshold-based Multi-layer Decision Feedback Equalizer - 36 - 3.1 System model - 36 - 3.2 2-layer STM-Algorithm - 37 - 3.2.1 2-layer STM Algorithm - 39 - 3.2.2 MAP Detection in Stage 2 - 40 - 3.2.3 Boundaries of Decision Regions in Stage 2 - 42 - 3.2.4 Optimal Threshold Value L for Minimizing BER - 44 - 3.3 Higher-order Layer of the STM Algorithm - 47 - 3.3.1 Detection Scheme in the N-layer STM Algorithm - 47 - 3.3.2 Calculation of Threshold Value in the N-layer STM Algorithm - 49 - 3.4 Operations of the STM Algorithm - 50 - 3.5 Numerical Analysis and Simulation Results - 51 - 3.6 STM-Engine - 57 - 3.6.1 Operations of the STM-Engine - 58 - 3.6.2 Low-cost Architecture of the STM-Engine - 59 - Chapter 4 High-speed VLSI architectures - 62 - 4.1 Review of the Implementation method of a DFE - 62 - 4.2 Precomputation Approaches for High-speed Applications - 65 - 4.2.1 Generalized Na-tap FBF - 65 - 4.2.2 Partial Precomputation Scheme - 66 - 4.2.3 Two-Stage precomputation Scheme - 69 - 4.3 High-speed Architecture of the STM-DFE - 72 - 4.3.1 Threshold Detector/ Data Detector Algorithm - 73 - 4.3.2 Threshold Detector/ Data Detector Architecture - 76 - 4.3.3 Overall System Architecture of the 2-Layer STM-DFE - 78 - 4.4 Precomputation-based LMS (PBLMS) Algorithm - 79 - 4.4.1 Precomputation-based LMS - 80 - 4.4.2 Learning Curve of the PBLMS - 81 - 4.4.3 VLSI Architecture of the PBLMS - 84 - Chapter 5 STM-DFE Design for 10GBase-LX4 Systems - 86 - 5.1 Simulation Environment of 10GBase-LX4 Systems - 87 - 5.1.1 Simulated Channel Configuration - 87 - 5.1.2 Analog Equalization in 10GBase-LX4 Systems - 90 - 5.2 Parameters Assignment for the STM-DFE - 93 - 5.2.1 Number of Taps in FFF and FBF - 93 - 5.2.2 Floating-point Analysis - 97 - 5.2.3 Fixed-point Analysis - 99 - 5.3 Simulation Results - 104 - 5.4 VLSI architecture - 107 - Chapter 6 Conclusions and Future Researches - 114 - | |
| dc.language.iso | en | |
| dc.title | 高性能迴饋決策等化器演算法及硬體架構設計 | zh_TW |
| dc.title | High-performance Decision Feedback Equalizer Algorithms and Architectures | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 曹恒偉,闕志達,王晉良,吳文榕,陳紹基,周世傑,黃穎聰 | |
| dc.subject.keyword | 迴饋決策等化器,10Gbase乙太網路, | zh_TW |
| dc.subject.keyword | STM-DFE,DFE,10Gbase LX4, | en |
| dc.relation.page | 121 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2005-06-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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