H.264/AVC熵解碼器之設計與實作

Abstract

H.264/AVC在編碼效能上比起之前的視訊壓縮標準有明顯的進步，在熵編碼上，採用了算數編碼和可變長度編碼。其中可變長度編碼的方法有別於之前視訊壓縮標準，具備了內容感知而使用不同的查表，另外，也加進了trailing ones的觀念， 其壓縮效能幾乎接近算數編碼而運算複雜度遠低於算數編碼。在通訊、電腦、多媒體發達的今日，視訊電話、視訊會議、電視極高畫質電視等，往往必須在極短的時間內處理龐大的資料。因此，效率高、品質高的影像壓縮與視訊壓縮技術是必須的。 在本論文中，我們提出了高生產率且適用於H.264/AVC baseline profile可變長度解碼電路設計與實作，並且結合了Exp-Golomb解碼器使的整個H.264/AVC baseline profile熵解碼器更為完整。由於在熵編碼上，其編碼是不定長度，所以在解碼上，必須前個係數先被解出來，才能知道下個係數該從位元流的哪個位置開始解碼，如此限制了對解碼電路利用管線或平行處理的電路技巧。我們觀察了可變長度解碼的幾個步驟，從查表的編排解碼方式和trailing ones編碼等特性，在不增加太多電路面積與最長路徑的合理範圍內，適當的增加每個時脈解出係數的個數，達到高生產率和提升解碼速度的目的，並且對所使用的查表進行適當的分類進而達到簡化電路的效果。 製作的CAVLC解碼器晶片是使用UMC 0.18μm 1P6M CMOS製程，所製作的晶片時脈可達71.43MHz，消耗功率約16.8707mW。在不失一般性情況下，每個block大約使用30個時脈可以解出全部係數。每個macroblock大約需480個時脈，在視訊標準中本論文之電路可以及時解出level 3.1的視訊，其大小為1280 x 720 每秒30張圖。

The coding performance of H.264/AVC has greater improvement than previous video standards. It adopts Context-Based Adaptive Binary Arithmetic Coding (CABAC) and variable length coding as its entropy coding. In variable length coding of H.264/AVC, context-based adaptive and trailing ones are the important coding skills to increase coding performance. Its compression rate is very close to CABAC but the computing complexity is much lower. With the recent development of communication, computer, and multimedia, the real-time processing of huge data is required for video phone, video conference and high definition television applications. So, high performance video compression technology is needed. In this Thesis, we propose a high throughput variable length decoder circuit for H.264/AVC baseline profile. A whole entropy decoder for H.264/AVC baseline profile is also presented. As the name indicates, codewords are of variable length. Furthermore, there is no boundary information for detecting the end or beginning of the codeword. These characteristics complicate the design and hardware realizations. We observe the coding steps and lookup tables of CAVLC. Then we propose a multiple-symbol decoder for CAVLC without increasing too many circuit area and critical path. A prototype chip is implemented to verify the design of proposed CAVLC decoder circuit. The chip is fabricated in UMC 0.18μm 1P6M CMOS process through CIC. The die size is 1.291 x 1.292 mm2, and gate count is about 10k. The maximum operation frequency obtained from gate level simulation is 100 MHz. And the maximum operation frequency from post layout simulation is 71.43 MHz. The format of test image is CIF. In general, the average number of total coefficients need to be decoded in one block is not over 5. In this condition, we can decode one block about 30 cycles. Thus, one macroblock (MB) decoding needs about 480 cycles to complete. In H.264 standard, Level 3.1 needs a maximum MB processing rate of 108,000 MB per second. That is, we need an operation frequency of 480x 108,000= 51,840,000 clocks/s=51.84 MHz, which is lower than our maximum post layout frequency. The format of processing image in Level 3.1 is 1280 x 720 x 30 fps. Power consumption of our design is about 16.8707mW at 1.8 V, and the number of pads is 58.