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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳敏璋(Miin-Jang Chen) | |
dc.contributor.author | Hsin-Jui Chen | en |
dc.contributor.author | 陳欣銳 | zh_TW |
dc.date.accessioned | 2021-06-08T05:24:56Z | - |
dc.date.copyright | 2011-08-04 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-28 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24409 | - |
dc.description.abstract | 本論文研究利用原子層沉積(Atomic Layer Deposition, ALD)技術應用於提升奈米級粗紋化矽晶太陽能電池效率。我們在矽晶表面製作奈米級粗紋化結構,在太陽光譜下產生較低之反射率,使得矽晶片的表面呈現黑色,我們稱之為黑色矽晶片。由於ALD技術可精確沉積單一原子層厚度之薄膜,為現今最先進之奈米薄膜沉積技術,因此近年來,ALD技術逐漸受到學術界與產業界廣泛的重視。ALD技術具有(1)原子等級控制材料的形成;(2)精準控制薄膜的厚度與成分;(3)大面積與批次型量產;(4)優異的均勻度;(5)優異的三維包覆性;(6)無孔洞結構、缺陷密度小;以及(8)沈積溫度較低等優點。本論文將原子層沉積技術與黑色矽晶片技術相結合,以提高黑色矽晶片太陽能電池元件的效率,效率分別可達14.43%與17.24%。 | zh_TW |
dc.description.abstract | In this thesis, we report the efficiency enhancement of nanotextured silicon solar cells by atomic layer deposition (ALD). Nanotextured structures were fabricated on the surface on silicon substrates to reduce the reflectance. Thus the silicon wafers exhibit very low reflectance in sunlight spectrum and are called “black silicon wafers”. ALD technique offers many advantages, including easy and accurate thickness control, excellent conformality, low defect density, high uniformity over a large area, good reproducibility, and low growth temperatures. Nanotextured silicon wafers together with the ALD techniques were applied to enhance the efficiency of silicon solar cells in this study. Efficiencies up to to 14.43% and 17.24% were realized in the nanotextured silicon solar cells, respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:24:56Z (GMT). No. of bitstreams: 1 ntu-100-R98527059-1.pdf: 1920223 bytes, checksum: 17e1e49efbdea62f10b3ce1262acc579 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 口試委員審定書 I
誌謝…. II 摘要…. III Abstract IV 目錄…. V 圖目錄 …………………………………………………………………………..…...VIII 表目錄. XI 第一章 緒論 1 1.1 研究動機 1 1.2 原子層沉積技術之原理與特性 2 1.3 參考文獻 6 第二章 黑晶片之製作與黑晶片太陽能電池元件 8 2.1 簡介 8 2.2 黑晶片製程介紹 10 2.3 實驗 11 2.3.1黑晶片性質分析 11 2.3.2黑晶片太陽能電池元件製備與量測 11 2.3.3 黑晶片太陽能電池轉換效率量測 13 2.4 結果與討論 14 2.4.1 掃描式電子顯微鏡觀測 14 2.4.2 反射率量測 14 2.4.3 黑晶片太陽能電池 19 2.4.4 背面表面電場 20 2.5結論 25 2.6 參考文獻 26 第三章 利用原子層沉積技術成長表面鈍化層應用在 黑晶片太陽能電池元件上 29 3.1 簡介 29 3.2 實驗 31 3.2.1 利用原子層沉積技術成長氧化鋁、氧化鎂、氧化鋯 31 3.2.2 含有表面鈍化層之黑晶片太陽能電池元件製程 33 3.2.3 黑晶片太陽能元件轉換效率量測 33 3.3 結果與討論 34 3.3.1 成長表面鈍化層的原因與材料選擇 34 3.3.2成長氧化鋁作為表面鈍化層 36 3.3.3 成長氧化鎂作為表面鈍化層 42 3.3.4 成長氧化鋯作為表面鈍化層 43 3.3.5 複合薄膜作為表面鈍化層 44 3.4 結論 46 3.5參考文獻 48 第四章 利用氧化鋅奈米柱陣列作為抗反射層應用在一般矽晶太陽能電池上 51 4.1 簡介 51 4.2 實驗 53 4.2.2 氧化鋅奈米柱性質分析 54 4.2.3 氧化鋅奈米柱陣列作為抗反射層之太陽能電池元件製作 55 4.2.4 黑晶片太陽能元件轉換效率量測 56 4.3 結果與討論 57 4.3.1 SEM圖與反射率 57 4.3.2 一般矽晶元件效率量測 60 4.3.3 成長氧化鋁作為表面鈍化層之元件效率量測 61 4.3.4 成長氧化鋅薄膜作為抗反射層之元件效率量測 61 4.3.5 成長氧化鋅奈米柱陣列作為抗反射層之元件效率量測 62 4.4 結論 64 4.5參考文獻 65 第五章 總結 69 | |
dc.language.iso | zh-TW | |
dc.title | 利用原子層沉積技術提升奈米級粗紋化矽晶太陽能電池效率之研究 | zh_TW |
dc.title | Efficiency Enhancement of Nanotextured Silicon Solar Cells by Atomic Layer Deposition | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 徐文慶,郭錦龍,陳景翔 | |
dc.subject.keyword | 原子層沉積技術,矽晶太陽能電池,黑色矽晶片, | zh_TW |
dc.subject.keyword | atomic layer deposition,silicon solar cell,black silicon wafer, | en |
dc.relation.page | 70 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2011-07-28 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
顯示於系所單位: | 材料科學與工程學系 |
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