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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24221完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷 | |
| dc.contributor.author | Huan-Sheng Li | en |
| dc.contributor.author | 黎煥昇 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:18:53Z | - |
| dc.date.copyright | 2005-08-12 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-29 | |
| dc.identifier.citation | [1] R.G. Gallagher, “Low-density parity-check codes,” IRE Trans. on Info. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
[2] D.J.C. MacKay and R.M. Neal, ‘’Good code based on very sparse matrices,” in Cryptography and Coding, 5th IMA Conference. Lecture Notes in Computer Science. vol. 1025, C. Boyd, Ed. Berlin, Germany: Springer, 1995, pp. 100-111. [3] D.J.C. Mackay and R.M. Neal, “Near Shannon limit performance of low density parity check codes,” IEE Electronics Letters, vol. 33, no.6, pp. 457-458 [4] Wei, L., “Several Properties of Short LDPC Codes,” IEEE Transactions on Communications, vol. 52, no. 5, pp.721-727, May. 2004 [5] Lu, J; Moura, J.M.F., “Turbo design for LDPC codes with large girth,” Signal Processing Advances in Wireless Communications, 2003. SPAWC 2003. 4th IEEE Workshop on, pp.15-18, June. 2003 [6] Lu, J; Moura, J.M.F.; Niesen, U.,”A class of structured LDPC codes with large girth,” Communications, 2004 IEEE International Conference, vol.1, no. 20-24, pp. 425-429, June. 2004 [7] Haotian Zhang; Moura, J.M.F., “The Design of Structured Regular LDPC Codes With Large Girth,”Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE , vol. 7, pp. 4022 – 4027, no.1-5, Dec. 2003 [8] Campello, J.; Modha, D.S. “Extended Bit-Filling and LDPC Code Design,” IEEE Global Telecommunications Conference 2001 GLOBECOM '01, vol. 2, no. 25-29, pp. 985 – 989, Nov. 2001 [9] F.R. Kschischang and B.J. Frey, “Iterative decoidng of compound codes by probability propagation in graphical models,” IEEE J. Select. Areas Commun., vol. 16, pp. 219-230, Feb. 1998. [10] Fossorier, M.P.C., ”Quasi-cyclic low-density parity-check codes from circulant permutation matrices,” IEEE Transactions on Information Theory, vol. 50, no. 8, pp.1788 – 1793, Aug. 2004 [11] D. Sridhara, T. E. Fuja, and R. M. Tanner, “Low density parity check codes from permutation matrices,” in Proc. Conf. Information Sciences and Systems, Baltimore, MD, pp. 142, Mar. 2001 [12] R. M. Tanner, “Minimum distance bounds by graph analysis,” IEEE trans. Inform. Theory, vol. 47, pp. 808-821, Feb. 2001. [13] D. J. C. MacKay and M. C. Davey, Evaluation of Gallager Codes for Short Block Length and High Rate Applications, 2001, vol. 123, IMA volumes in Mathematics and its Applications, ch. 5, pp. 113-130. [14] Shu Lin, Lei Chen, Jun Xu, Djurdjevic L.,”Near Shannon limit quasi-cyclic low-density parity-check codes,” IEEE Global Telecommunications Conference2003 GLOBECOM '03, vol. 4, no. 1-5, pp. 2030 – 2035, Dec. 2003 [15] Genetic Algorithm website, http://lancet.mit.edu/ga/ [16] D. E. Golderg, Genetic Algorithm in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc. Boston, MA, USA, 1989. [17] Tanner, R.M.; Sridhara, D.; Sridharan, A.; Fuja, T.E.; Costello, D.J., Jr., “LDPC Block and Convolutional Codes Based on Circulant Matrices,” IEEE Transactions on Information Theory, vol. 50, no. 12, pp. 2966 – 2984, Dec. 2004 [18] European Telecommunications Standards Institude (ETSI). Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite application; EN 302 307 V1.1.1. www.dvb.org [19] H. Jin, A. Khandekar, and R. McEliece. “Irregular Repeat Accumulate Codes,” In Proc. 2nd International Symposium on Turbo Codes & Related Topics, pp. 1-8, Brest, France, Sep. 2000 [20] T. Tian, C. Jones, and D. Villasenor, “Rate-Compatible Low-Density Parity-Check Codes,” Proceedings of the International Symposium on Information Theory, June 2004. [21] Tong Zhang and Keshab K. Parhi,”A 54 MBPS (3,6)-Regular FPGA LDPC Decoder,” Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on , pp. 127 -132, Oct. 2002 [22] Tong Zhang; Parhi, K.K., “Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design,” IEEE Transactions on Signal Processing [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on], vol. 52, no. 4, pp. 1065 - 1079, April. 2004 [23] Yanni Chen; Parhi, K.K., ”Overlapped message passing for quasi-cyclic low-density parity check codes,” Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on], vol. 51, no. 6, pp.1106 – 1113, June. 2004 [24] Yongyi Mao; Banihashemi, A.H., “A Heuristic Search for Good Low-Density Parity-Check Codes At Short Block Length”, IEEE International Conference on Communications, 2001. ICC 2001, vol.1, no. 11-14, pp. 41 – 44, June. 2001 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24221 | - |
| dc.description.abstract | Gallager’s Low-Density Parity-Check (LDPC) codes have recently received a lot of attention because of their excellent performance and low decoding complexity. Since that the hardware complexity is lower than that of Turbo codes, LDPC codes have been widely considered as next-generation error-correcting codes for many real-word applications. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. This thesis presented a genetic algorithm (GA) based regular quasi-cyclic LDPC code search algorithm with hardware and coding gain considerations. Hardware constraint, average girth and bit error rate simulation are used as criterions to select the best code candidates in GA algorithm. An efficient LDPC matrix representation is proposed for the GA algorithm. The results show that our algorithm can efficiently pick hardware implementation friendly LDPC codes with good coding gain performance. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:18:53Z (GMT). No. of bitstreams: 1 ntu-94-R92922084-1.pdf: 1787206 bytes, checksum: f1c89e60eb026eedd057f107b45daa05 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | ABSTRACT 1
1. INTRODUCTION 2 1.1. DIGITAL COMMUNICATION SYSTEM OVERVIEW 2 1.2. LOW DENSITY PARITY CHECK CODE 3 1.2.1. LDPC Code Construction 3 1.2.2. Encoding 5 1.2.3. Girth 6 1.2.4. Minimum Distance 7 1.2.5. Decoding 7 1.3. REGULAR QUASI-CYCLIC LDPC CODE 8 1.3.1. Regular Quasi-cyclic LDPC Code Construction 8 1.3.2. The Upper Bound of Girth 9 1.3.3. The Upper Bound of Minimum Distance 11 1.3.4. Redundant Check 12 2. RELATED WORKS 15 2.1. ALGEBRAIC CONSTRUCTED LDPC CODE 15 2.2. DVB-S2 LDPC CODE 16 2.3. RATE-COMPATIBLE LDPC CODE 18 2.4. CONVOLUTIONAL LDPC CODE 20 3 HARDWARE ISSUES 21 3.1 THE HARDWARE ARCHITECTURE OF LDPC DECODER 21 3.2 OVERLAPPED DECODING ALGORITHM 22 3.3 MULTITHREAD DECODING ALGORITHM 25 3.3.1 Scalable Factor Effect 25 4 HARDWARE-AWARE GA-BASED LDPC CODE SEARCH 27 4.1 GENETIC ALGORITHM OVERVIEW 27 4.2 GA-BASED LDPC CODE SEARCH 29 4.2.1 GA Encoding 29 4.2.2 Population 29 4.2.3 Hardware-oriented Constraint 30 4.2.3.1 Overlapped Decoding Constraint 30 4.2.3.2 Multithread Decoding Constraint 31 4.2.4 Performance-oriented Constraint 31 4.2.4.1 Average Girth 31 4.2.4.2 Bit Error Rate 32 4.2.5 Crossover 32 4.2.6 Mutation 32 4.2.7 Two Phases Section Strategy 32 4.2.8 GA Code Search Procedure 33 5 SIMULATION RESULTS 35 5.1 SIMULATION 1 35 5.2 SIMULATION 2 36 5.3 SIMULATION 3 37 5.4 SIMULATION 4 38 5.5 SIMULATION 5 39 5.6 SIMULATION 6 40 5.7 SIMULATION 7 41 5.8 SIMULATION 8 42 6 CONCLUSION AND FURTURE WORK 43 7 APPENDIX 44 7.1 PARAMETERS OF ALGEBRAIC CONSTRUCTED QC CODE 44 7.2 GA CODE SEARCH SIMULATED PROGRAM 46 7.2.1 Flow Chart of GA Code Search 46 7.2.2 Module Description 47 7.3 BRUTE FORCE CODE SEARCH SIMULATED PROGRAM 50 7.3.1 Flow Chart of Brute Force Code Search 50 7.3.2 Module Description 51 REFERENCE 52 | |
| dc.language.iso | en | |
| dc.title | 硬體實作取向正規類迴旋低密度奇偶校驗碼之基因搜尋演算法 | zh_TW |
| dc.title | Hardware-Aware GA-Based Regular Quasi-Cyclic LDPC Code Search Algorithm | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪士灝,黃鐘揚,廖俊睿 | |
| dc.subject.keyword | 類迴旋低密度奇偶校驗碼,圍長,基因演算法,重疊解碼,多重執行緒解碼, | zh_TW |
| dc.subject.keyword | QC-LDPC,Girth,GA,Overlapped decoding,Multithread decoding, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2005-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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| ntu-94-1.pdf 目前未授權公開取用 | 1.75 MB | Adobe PDF |
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