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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24150完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇 | |
| dc.contributor.author | Shih-Hung Chang | en |
| dc.contributor.author | 張世鴻 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:17:06Z | - |
| dc.date.copyright | 2006-01-26 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-01-17 | |
| dc.identifier.citation | [1] “IBM On-chip CoreConnect Bus Architecture White Paper.” http://www-306.ibm.com/chips/products/coreconnect/index.html.
[2] “ARM Advanced Microcontroller Bus Architecture (AMBA) specification rev 2.0.” http://www.arm.com/products/solutions/AMBA_Spec.html. [3] Shinji Kimura, et al, “An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators,” ISSCC Digest of Technical Papers, pages 390-391, 2003. [4] M. Sgroi, et al, “Addressing the system-on-a-chip interconnect woes through communication-based design,” Proceedings Design Automation Conference, pages 667-672, 2001. [5] Michael Bedford Taylor, et al, “The Raw Microprocessor: A computational fabric for software circuits and general-purpose programs,” IEEE MICRO, vol. 22, no. 2, 2002. [6] William J. Dally and Brian Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proceedings Design Automation Conference, 2001. [7] X. Zhu and S. Malik “A Hierarchical Modeling Framework for On-Chip Communication Architectures,” ICCAD IEEE/ACM International Conference on Computer Aided Design, pages 663-670, 2002. [8] Se-Joong Lee, et al, “An 800MHz Stat-Connected On-Chip Network for Application to Systems on a chip,” ISSCC Digest of Technical Papers, pages 468-469, 2003. [9] “晶片內傳輸矽智產之原型設計和硬體實現”, 張龍豪, 國立台灣大學電機工程研究所碩士論文,中華民國九十三年七月. [10] L. Carloni, A. L. Sangiovanni-Vincentelli, “On-chip communication design: roadblocks and avenues,” in Proc. Int. Symp. HW/SW Codesign, Oct, 2003. [11] G.. M. Jacobs, R. W. Broderson, “A fully asynchronous digital signal processor using self-timed circuits,” IEEE J. Solid-State Circuits, vol.25, no.6, Dec.1990, pp.1526-1537. [12] Jens Muttersbach, et al, “Practical design of globally-asynchronous locally-synchronous system,” Proceedings International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 52-59, 2000. [13] Thomas Villiger, et al, “Self-timed Ring for Globally-Asynchronous Locally-Synchronous Systems,” Proceedings International Symposium on Asynchronous Circuit and Systems, pages 141-150, 2003. [14] S. J. Jou, I.Y. Chuang, “Low-Power Globally Asynchronous Locally Synchronous Design Using Self-Timed Circuit Technology,” in Proc. IEEE International Symposium on Circuits and Systems, vol. 3, pp.1808-1811, June 1997. [15] J. Muttersbach, Villiger, et al, “Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems,” Proceedings. ASIC/SOC Conference, pp.317-321, Sept 1999. [16] L. Wu, et al, “A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver,” in Proc. IEEE International Symposium on Circuits and Systems, vol. 2, pp.565-568, May 1999.. [17] H. Braunisch, et al, ”On the techniques of clock extraction and oversampling,” Hot Interconnects 9, pp.139-143, Aug 2001. [18] Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo, ”SILENT: serialized low energy transmission coding for on-chip interconnection networks,”ICCAD, 2004. [19] S. Sidiropoulos,and M.Horowitz,” A semidigital dual delay-locked loop,” IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp.1683 –1692, Nov. 1997. [20] R. Farjad-Rad, et al, ”A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, pp.1804–1812, Dec 2002. [21] S. J. Jou, C. H. Lin, T. H. Chen and Z. H. Li, “Module Generator of Data Recovery Circuits Using Oversampling Technique,” IEEE International SOC Conference, Sept, 2003, pp.95-98. [22] T.-Y. Hsu, C.-C. Wang, and C.-Y. Lee,”Design and analysis of a portable highi-speed clock generator,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 367-375, Apr. 2001. [23] Ron Ho, et al, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pages 490-504, 2001. [24] V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, “Clock rate versus ipc: The end of the road for conventional microarchitectures,” In 27th Annual Intl. Symposium on Computer Architecture, pages 248-259, June 2000. [25] E. Roth, M. Thalmann, N.Felber, W.Fichtner, “A delay-line based DCO for multimedia applications using digital standard cells only”, ISSCC Digest of Technical Papers, pages 432 - 505 , 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24150 | - |
| dc.description.abstract | 系統晶片(System-on-chip)積體電路的晶片內聯結方法有兩種類型，第一種是採用共用匯流排的架構來連接所有的元件，這是系統單晶片積體電路最常使用的方法。第二種是以序列傳輸(Serial transmission)的方式做為晶片內資料傳輸的架構。然而當製程進步到0.18微米以下，使用匯流排的架構會有大量的繞線面積、嚴重的信號偶合和劇烈的接線延遲等問題，這些問題造成積體電路設計上的困難，所以，我們採用序列傳輸的方式來做為實體層的連結方法。但是我們之前的解決方法並不是只有單一接線，而是會有兩條接線，在大型複雜的系統單晶片中，要控制兩條接線的傳輸延遲和信號的互相干擾是很困難的，因此，本論文提出以時脈及資料回復技術來實現晶片內的序列傳輸電路。
未來的系統單晶片中資料的傳送，已經不再是如傳統的解決邏輯功能的運算，而是演變成通訊的問題，本論文提出以通訊系統中常用的時脈及資料回復技術為基礎，設計出適合於系統單晶片的序列傳輸電路。這個技術在實體電路上只有單一接線，除了解決了兩條接線的傳輸延遲和信號的互相干擾的問題，同時，也降低了繞線的複雜度。最後，本論文採用聯電0.18微米1P6M製程來分別實現傳送端和接收端的電路，電路面積分別為93um*91um及140um*140um，再整合成一個序列傳輸的電路。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:17:06Z (GMT). No. of bitstreams: 1 ntu-95-P92943001-1.pdf: 924546 bytes, checksum: 11529aa0efad48f4973c5d530b5d071a (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Abstract xix
Contents xxi List of Figures xxiii List of Tables xxv Chapter 1 Introduction 1 1.1 Motivation and Goal 3 1.2 Thesis outline 4 Chapter 2 Serial Transmitting Architecture 6 2.1 Overview of Serial Transmitting Architecture 8 2.2 Analysis of Serial Transmitting Architecture 11 2.3 Overview of Clock and Data Recovery 14 Chapter 3 The Architecture of Proposed CDR-Based On-Chip Communication 18 3.1 Transmitter Architecture 19 3.2 Receiver Architecture 20 3.3 Wire Load Model 31 3.4 Transceiver Architecture 34 3.5 Comparison 35 Chapter 4 Simulation Results 39 4.1 DCO Simulation 39 4.2 Permissible Range of Different Frequency 41 4.3 Transmitter and Receiver 44 4.4 Serial Transmission Circuit 46 Chapter 5 CHIP Implementation 48 5.1 Transmitter and Receiver 48 5.2 Realization of On-Chip Serial Transmission Circuit 50 Chapter 6 Conclusions 53 Reference 54 | |
| dc.language.iso | zh-TW | |
| dc.subject | 序列傳輸電路 | zh_TW |
| dc.subject | serial transmission circuit | en |
| dc.title | 以數位式時脈及資料回復技術實現之晶片內序列傳輸電路 | zh_TW |
| dc.title | On-chip Serial Transmission Circuits Based on Digital CDR Approach | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳政勳,曹恆偉,林宗賢 | |
| dc.subject.keyword | 序列傳輸電路, | zh_TW |
| dc.subject.keyword | serial transmission circuit, | en |
| dc.relation.page | 55 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-01-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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