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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | |
dc.contributor.author | Shian-Hau Liao | en |
dc.contributor.author | 廖顯皜 | zh_TW |
dc.date.accessioned | 2021-06-08T05:14:40Z | - |
dc.date.copyright | 2006-07-18 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-06-28 | |
dc.identifier.citation | [1] W.Mueller, G.Aichmayr, W.Bergner, M.Goldbach, T.Hecht, S.Kudelka, F.Lau*, J.Nuetzel, A.Orth, T.Schloesser, A.Scholz, A.Sieck, A.Spitzer*, M.Strasser*, P.-F.Wand, S.Wege, R.Weis “Trench DRAM Technologies for the 50nm Node and Beyond” 1-4244-0182-8 pp. 92-93, 2006 IEEE VLSI-TSA.
[2] S.H. Hong, B.Y. Koo, T.S. Jeon, S.J. Hyun, Y.G. Shin, U-In. Chung and J.T. Moon “Low Voltage (1.2V) and High Performance Mobile DRAM Device Technology with Dual Poly-silicon Gate using Plasma Nitrided Gate oxide” pp.441-444, 2004 IEEE. [3] S.H. H0ng.T.S. Jeon, B.Y. Koo S.J. Hyun, Y.G. Shin, U-In. Chun and J.T. Moon “The develo ment of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMS: plasma process monitoring and the correlation with electrical results” 0-7803-8528-4 pp. 219-222, 2004 IEEE. [4] Daniel Chong, Won Jong Yo0 and Chun Meng Lek “Plasma Charging Damage Immunities of Rapid Thermal Nitrided Oxide and Decoupled Plasma Nitrided Oxide” 0-7803-7722-2, pp.141-145, Proceedings of 10th IPFA 2003, Singapore. [5] C.M. Lek, B.J. Cho, W.Y. Loh, C.H. Ang, Wenhe Lin, Y.L. Tan, J.Z. Zhen, Lap Chan, S.S. Tan, T.P. Chen “ Effects of Post-Decoupled-Plasma-Nitridation Annealing of Ultra-Thin Gate Oxide” 0-7803-7416-9, pp. 232-236, Proceedings of 9th IPFA 2002, Singapore. [6] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. F. Wang, Y. M. Lin, M. C. Yu, S. C. Chen, C. H. Yu, and M. S. Liang “High-Quality Ultrathin (1.6 nm) Nitride/Oxide Stack Gate Dielectrics Prepared by Combining Remote Plasma Nitridation and LPCVD Technologies” 0741-3106, pp. 260-262. IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 6, JUNE 2001. [7] H.-H. Tseng, Senior Member, IEEE, Y. Jeon, P. Abramowitz, T.-Y. Luo, L. Hebert, J. J. Lee, J. Jiang, P. J. Tobin,G. C. F. Yeap, Senior Member, IEEE, M. Moosa, J. Alvis, S. G. H. Anderson, N. Cave, T. C. Chua, A. Hegedus, G. Miner, J. Jeon, and A. Sultan “Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology” 0741-3106, pp. 704-705, IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 12, DECEMBER 2002. [8] C.M. Lek, B.J. Cho, W.Y. Loh, C.H. Ang, Wenhe Lin, Y.L. Tan, J.Z. Zhen, Lap Chan, S.S. Tan, T.P. Chen “ Effects of Post-Decoupled-Plasma-Nitridation Annealing of Ultra-Thin Gate Oxide” 0-7803-7416-9, pp. 232-236, Proceedings of 9th IPFA 2002, Singapore. [9] Vincent S. Chang, C.C. Chen, C.L. Wu, D.Y. Lee, T.L. Lee, S.C. Chen, M.S. Liang, “Effects of Plasma-induced Damage to Ultrathin (<1.5nm) Gate Dielectric on Equivalent Oxide Thickness Downscaling Using Plasma Nitridation Process” 0-7803-7747-8, pp. 130-133, 2003 IEEE. [10] Won K. Park, Jung H. Lee, and Geun Lim “Effect of Capping Silicon Nitride Layer and Nitrided Gate Oxide on Hump of Transistors”, 0741-3106, pp. 532-534, IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 8, AUGUST 2004 [11] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. F. Wang, Y. M. Lin, M. C. Yu, S. C. Chen, C. H. Yu, and M. S. Liang “High-Quality Ultrathin (1.6 nm) Nitride/Oxide Stack Gate Dielectrics Prepared by Combining Remote Plasma Nitridation and LPCVD Technologies”, 0741-3106, pp. 260-262, IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 6, JUNE 2001 [12] Jin-Hwa Heo, Dong-Chan Kim, Bon-Young Koo, Ji-Hyun Kim, Chul-Sung Kim, Young-Jin Noh, Sung-Kweon Baek, Yu-Gyun Shin, U-In Chung, and Joo-Tae Moon, “Effects of Plasma Nitridation on the Electrical Properties of Nitrided Oxide Gate Dielectric for DRAM Application”, 0-7803-9205-1, PP. 205-208, Proceedings of ESSDERC, Grenoble, France, 2005. [13] Neal Sullivan, Laxminarayan L. Raja, Robert J. Kee, “Exploring ISSG Process Space” 9th Int. Conference on Advanced Thermal Processing of Semiconductors-RTP 2001. [14] T. Y. Luo, M. Laughery, G. A. Brown, Member, IEEE, H. N. Al-Shareef, V. H. C. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, “Effect of H2 Content on Reliability of Ultrathin In-Situ Steam Generated (ISSG) SiO2”, pp. 430-432, IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 9, SEPTEMBER 2000. [15] Tung-Ming Pan, Hsiu-Shan Lin, Main-Gwo Chen, Chuan-Hsi Liu, and Yih-Jau Chang, “Comparison of Electrical and Reliability Characteristics of Different 14Å Oxynitride Gate Dielectrics”, pp. 416-418, IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 7, JULY 2002. [16] Kevin J. Yang and Cheming Hu, “MOS Capacitance Measurements for High- Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, pp. 1500-1501, 1999. [17] Szu-Wei Huang, Jenn-Gwo Hwu, Senior Members, IEEE, “Electrical Characterization and Process Control of Cost-Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing”, 0018-9383, pp.1658-1664, IEEE TRANSCATIONS ON ELECTRON DEVICES, VOL.50, NO.7, JULY 2003. [18] P. Masson, et al., “On the Tunneling Component of Charge Pumping Current in Ultrathin Gate Oxide MOSFETs,” Elect. Dev. Lett., Vol. 20, No. 2, pp. 92-94, 1999. [19] Chung, Steve S., et al., “A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12~16Å) Gate Oxide,” 2002 VLSI Tech.Digest of Tech. Papers. [20] Chao-Chi HONG, Wei-Ren CHEN and Jenn-Gwo HWU, “Local Thinning-Induced Oxide Nonuniformity Effect on the Tunneling Current of Ultrathin Gate Oxide”, Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 1–4 Part1, No. 1, January 2002 [21] Giorgio Cellere, Member, IEEE, Luca Larcher, Member, IEEE, M. G. Valentini, and Alessandro Paccagnella, Member, IEEE, “Plasma-Induced Micro Breakdown in Small-Area MOSFETs”, 0018-9383, pp. 1768-1773, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 10, OCTOBER 2002. [22] You-Lin Wu and Shi-Tin Lin, “Two-Trap-Assisted Tunneling Model for Post-Breakdown I−V Characteristics in Ultrathin Silicon Dioxide”, 1530-4388, pp. 75-80, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006. [23] In-Ho Nam, Jae Sung Sim, Sung In Hong, Byung-Gook Park, Member, IEEE, Jong Duk Lee, Member, IEEE, Seung-Woo Lee, Man-Sug Kang, Young-Wug Kim, Kwang-Pyuk Suh, Member, IEEE, and Won Seong Lee, “Ultrathin Gate Oxide Grown on Nitrogen-Implanted Silicon for Deep Submicron CMOS Transistors” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 10, OCTOBER 2001. [24] Motaharul K. Mazumder, Member, IEEE, Akinobu Teramoto, Junko Komori, Masahiro Sekine, Satoru Kawazu, and Yoji Mashiko, “Effects of N Distribution on Charge Trapping and TDDB Characteristics of N O Annealed Wet Oxide”, 0018-9383, pp. 1121-1125, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 6, JUNE 1999. [25] D. L. Crook, “Method of Determining Reliability Screens for Time Dependent Reliability Breakdown,” Proceedings of the International Reliability Physics Symposium, p.1, (1979). [26] Jordi Suñé and Ernest Wu, “Statistics of Successive Breakdown Events for Ultrathin Gate Oxides” Tech. Dig. Int. Electron Devices Meet., p.147~150, (2002). [27] R. Degraeve, B. Kaczer, M. Houssa, G. Groeseneken, M. Heyns, J. S. Jeon, A. Halliyal, “Analysis of High Voltage TDDB Measurements on Ta2O5/SiO2 Stack” Tech. Dig. Int. Electron Devices Meet., p. 327-330, (1999). [28] G. Ghidini, D. Brazzelli, C. Clementi, and F. Pellizzer, “Charge Trapping Mechanism under Dynamic stress and its Effect on Failure Time”, Proc. of IRPS, p88 (1999) [29] S. Ogawa, M. Shimaya, and N. Shiono, “Impact of negative-bias temperature instability on the lifetime of single-gate CMOS structures with ultrathin (4–6 nm) gate oxides,” Jpn. J. Appl. Phys., vol. 35, pp. 1484–1490, 1996. [30] S. Ogawa and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO interface,” Phys. Rev. B, vol. 51, pp. 4218–4230, 1995. [31] T. Yamamoto, K. Uwasawa, and T. Mogami, “Bias temperature instability in scaled p polisilicon gate p-MOSFETs,” IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 921–926, May 1999. [32] P. F. Schmidt and W. Michel, “Anodic formation of oxide films on silicon,” J. Electrochem. Soc., vol. 104, 230, 1957. [33] P. F. Schmidt, T. W. O’Keeffe, J. Oroshnik, and A. E. Owen, “Doped anodic oxide films for device fabrication in silicon: diffusion sources of controlled composition, and diffusion results,” J. Electrochem. Soc., vol. 112, no. 8, pp. 800-807, 1965. [34] G. C. Jain, A. Prasad and B. C. Chakravarty, “On the mechanism of the anodic oxidation of Si at constant voltage,” J. Electrochem. Soc., vol. 126, no. 1, pp. 89-92, 1979. [35] S. K. Sharma, B. C. Chakravarty, S. N. Singh, B. K. Das, D. C. Parashar, J. Rai and P. K. Gupta, “Kinetics of growth of thin anodic aoxides of silicon at constant voltages,” J. Phys. Chem. Solids, vol. 50, no. 7, pp. 679-684, 1989. [36] J. A. Bardwell, N. Draper, and P. Schmuki, “Growth and characterization of anodic oxides on Si(100) formed in 0.1 M hydrochloric acid,” J. Appl. Phys., vol. 79, no. 11, pp.8761-8769, 1996. [37] Vitali Parkhutik, “New effects in the kinetics of the electrochemical oxidation of silicon,” Electrochimica Acta, vol. 45, pp. 3249-3254, 2000 [38] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical properties of SiO2 thin films obtained by anodic oxidation,” Journal of Molecular Structure, pp. 607-610, 1999.” | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24041 | - |
dc.description.abstract | 為了達到快速及低耗電之元件,減少閘極氧化層厚度是現代超大型積體電路工程的一個主流。在傳統的動態隨機存取記憶體製程中,p型金氧半場效電晶體(pMOSFETs)用的是n+ 2多晶矽閘極以節省製程步驟及成本,但使用通道離子佈植(channel implant)以求CMOS臨界電壓匹配會形成深埋通道(buried channel)而降低速度。若為求更高速的動態隨機存取記憶體元件,改採用p+ 多晶矽閘極,則其中”硼離子穿透效應”(boron penetration)的問題將影響超薄閘極氧化層之元件特性。目前有許多方法可抑制”硼離子穿透效應”(boron penetration)的問題,其中使用去耦電漿氮化閘極氧化層是目前最有效方法之一。因此本論文將討論去耦電漿氮化閘極氧化層之元件特性。
第一章將針對使用去耦電漿氮化閘極氧化層之背景以及實驗規劃做個簡介,包含元件的製程內容、元件結構及量測儀器,以註明本實驗之過程。 第二章將探討氮化閘極氧化層之厚度之量測方法,包含光學量測、X光量測及顯微鏡量測。在藉由去耦離子製程功率調整植入不同的氮離子濃度,本研究利用SIMS分析氮離子在閘極氧化層內之濃度對深度分布曲線圖及利用XPS分析氮原子相對於氧原子之比率。 第三章將分析去耦氮化閘極氧化層之電容-電壓關係,量測不同頻率下的閘極電容,並從中可得到隨著改變植入氮離子濃度來觀察電容增大的效應、平帶電壓變動和相對界面缺陷電荷密度結果;之後研究電流-電壓關係,觀察電流增大的機制,並提出局部變薄效應(Local thinning effect)和缺陷輔助穿邃(trap assisted tunneling)效應來解釋氮離子植入增大電流的原因。最後將針對氮化閘極氧化層之可靠度進行測試,在持續電壓和持續電流加壓下,來探討其崩潰機制、電容衰減及電流穿透等特性。 最後,第四章是本論文之結論及未來工作建議。 | zh_TW |
dc.description.abstract | To obtain high speed and low power consumption device, the gate oxide thickness shrinkage is a main stream in modern VLSI industry. In conventional DRAM process, n+ poly gate is used for pMOSFETs to save process steps and cost. However, it generally needs p-type implant (boron, BF2) for threshold voltage (Vt) adjustment for CMOS technology. The implant leads p-channel far away from surface, and therefore results in the so called buried channel. The p+ poly gate will be adopted for pMOSFETs to gain high speed DRAM device. It induces “boron penetration” from the p+ doped poly gate to the cannel through the thin gate oxide. It is well known that boron penetration causes degradation of device performance. In order to block boron penetration, nitrided gate oxides formed by decoupling plasma nitridation (DPN) are good candidates to meet the target. In this thesis, we are going to discuss the characteristics of DPN nitrided gate oxide.
Chapter 1 is an introduction of DPN nitrided gate oxide experiment. The process flow design, device structure and measurement tool are also introduced to realize this experiment. Chapter 2 is a discussion for metrology of physical thickness, nitrogen concentration and profile in ntrided gate oxide. The analysis methods are including optical ellipsometer, XPS, TEM, SEM, TOF-SIMS and so on. Chapter 3 is the electrical characteristics of nitrided gate oxide. The C-V curves are extracted by various frequencies to compare VFB shift, CET, Dit with nitrogen. It is explained that the leakage current increases with nitrogen by “local thinning effect” and “trap assisted tunnel”. Finally, it is of importance to examine the reliability of nitrided gate oxide by CCV and CCS. The mechanism of breakdown is discussed via the TZDB and TDDB tests. The leakage increase and capacitance degradation are also discussed by SILC and NBTI. Finally, the conclusion and suggestion for future work are given in Chapter 4. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:14:40Z (GMT). No. of bitstreams: 1 ntu-95-P93943010-1.pdf: 1534750 bytes, checksum: f64b2624cb835aaff1ac573b9df07a9a (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | Chapter 1 Introduction ………………………………………1
1-1 Background …………………………………………1 1-2 Process flow and MOS device structure ……………2 1-3 Decoupling Plasma Nitridation (DPN) tool and process introduction …3 1-4 Measurement tool introduction …………………………… 4 Chapter 2 The Physical Characteristics of Nitrided Gate Oxides by DPN………………………………………………………14 2-1 The thickness of nitrided gate oxides with various nitrogen concentrations ………………………………15 2-2 Control of nitrogen distribution and concentration in nitrided gate oxides …………………… 16 2-3 The reaction mechanism of in-situ steam generation (ISSG) oxide… 19 2-4 Summary ………………………………………………20 Chapter 3 The Electrical Characteristics of Nitrided Gate Oxides by DPN………………………………………………………30 3-1 The electrical properties of nitrided gate oxides extracted from C-V curves ………………………………………30 3-1-1 Capacitance-Voltage (C-V) behavior of nitrided gate oxides with different DPN ………………………………………31 3-1-2 Interface trap density as extracted by two frequency C-V and charge pumping method …………………………………34 3-2 The electrical properties of nitrided gate oxides extracted from I-V curves ……………………………………37 3-3 The reliability performance of nitrided gate oxides by DPN after constant voltage stress (CVS) and constant current stress (CCS)………………… 39 3-3-1 Time Zero Dielectric Breakdown (TZDB) characteristics …………39 3-3-2 Time Dependence Dielectric Breakdown (TDDB) characteristics by CVS ……………………………………………40 3-3-3 Stress Induced Leakage Current (SILC) characteristics of nitrided gate oxides by CCS ……………44 3-3-3 Negative Bias Temperature Instability (NBTI) characteristics of nitrided gate oxides by CCS ……………45 3-4 Summary …………………………………………………………47 Chapter 4 Conclusion and Suggestions for Future Work ……78 4-1 Conclusion …………………………………………………… 78 4-2 Suggestions for Future work …………………………… 79 References ……………………………………………………………81 | |
dc.language.iso | en | |
dc.title | 去耦電漿氮化閘極氧化層之元件特性 | zh_TW |
dc.title | The Characteristics of MOS Devices with Nitrided Gate Oxide by Decoupling Plasma Nitridation | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 王維新,洪志旺,鄭晃忠 | |
dc.subject.keyword | 金氧半電容,氮化閘極氧化層, | zh_TW |
dc.subject.keyword | MOS,Nitrided gate oxide, | en |
dc.relation.page | 88 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2006-06-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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