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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23982完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Tzu-Chen Yang | en |
| dc.contributor.author | 楊子震 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:13:30Z | - |
| dc.date.copyright | 2006-07-21 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-15 | |
| dc.identifier.citation | [1] “Spread Spectrum Timing for Hard Disk Drive Applications,” http://www.cypress.com, Nov. 2000.
[2] “Intel® Pentium® 4 Processor in the 423-pin package EMI Guideline,” http://www.intel.com, Oct. 2000. [3] http://www.fulcrum.ru/Documents/CDROMs/NS/htm/nsc00596.htm. [4] S. Bolger and S. O. Darwish, “Use spread-spectrum techniques to reduce EMI,” EDN, vol.43, May 1998. [5] H. H. Chang, I. H. Hua and S. I. Liu, 'A spread spectrum clock generator with triangular modulation,' IEEE J. Solid-State Circuits, vol. 38, pp. 673-676, Apr. 2003. [6] F.M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Communications, vol.28, no.11, pp.1849-1858, Nov. 1980. [7] W.O. Keese, “An analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops,” National Semiconductor Application Note, no. 1001, May 1996. [8] K. Hardin et al. “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, pp. 227-231, Aug. 1994. [9] F. Lin and D.Y. Chen, “Reduction of Power Supply EMI Emission by Switching Frequency Modulation,” The VPEC Tenth Annual Power Electronics Seminar, Virginia Power Electronics Center, Blacksburg, Virginia, pp. 20-22, Sept. 1992. [10] K. B. Hardin and J. T. Fessler, “An Introduction of Spread Spectrum Clock Generation for EMI Reduction,” Electronic Engineering, vol. 71, no. 867, pp. 75, Apr. 1999. [11] H. S. Black.” Modulation Theory,” D. Van Nostrand Company, Inc., Princeton, 67 NJ, Bibliography, 1953. [12] J. Michel and C. Neron, “A Frequency Modulated PLL for EMI Reduction in Embedded Application,” Proc. IEEE Int. ASIC/SOC Conf, pp. 362-265, Sept. 1999. [13] H. Li et al., “Dual-Loop Spread-Spectrum Clock Generator,” IEEE ISSCC, pp. 184-185, Feb. 1999. [14] Y. Moon et al., “Clock Dithering for Electromagnetic Compliance Using Spread-Spectrum Phase Modulation,” IEEE ISSCC, pp. 186-187, 459, Feb. 1999. [15] “Jitter in PLL-Based Systems: Causes, Effects, and Solutions,” http://www.cypress.com, July 1997. [16] M. T. Zhang, “Notes on SSC and Its Timing Impacts,” http://www.intel.com, Feb. 1998. [17] H. H. Chang, I. H. Hua and S. I. Liu, ”A Shifted-Averaging VCO with Precise Multiphase Outputs and Low Jitter Operation,” ESSCIRC, Vol.16-18, pp.647 – 650, Sept. 2003. [18] J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [19] W. Rhee, ”Design of high-performance CMOS charge pump in phase-locked loops,” IEEE ISCAS, vol. 2, pp. 545-548, June 1999. [20] H.Y. Huang, S.F. Ho and L.-W. Huang, “A 64-MHz~1920-MHz Programmable Spread-Spectrum Clock Generator,” IEEE ISCAS, vol. 4, pp.3363-3366, May 2005. [21] S.T. Lee, S.J. Fang, D.J. Allstot, ” A 1.5V 28mA Fully-Integrated Fast-Locking Quad-Band GSM-GPRS Transmitter with Digital Auto-Calibration in 130um CMOS,” IEEE ISSCC, no. 10.4, Feb. 2004. [22] C. Vaucher and D. Kasperkovitz, “a wide-band tuning system for fully integrated satellite receivers ” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 987-997, July. 1998. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23982 | - |
| dc.description.abstract | 在現今的積體電路設計中，系統單晶片(SoC)是一個主流方向。鎖相迴路及相關的電路更是必須朝向SoC方面發展。隨著製程進步，電晶體的尺寸越來越小但對於被動元件的尺寸來說沒有變小。低通濾波器是鎖相迴路其中的一個區塊，是由電容以及電阻所組成。在過去的幾年中，為了降低晶片面積跟成本通常將低通濾波器設計在晶片外部。為了達到SoC的目的，希望將迴路濾波器整合進入晶片當中。然而，這些迴路濾波器在晶片當中佔了相當大的面積。由於在展頻時脈產生器中，通常會有一個較小的頻寬。所以在較小的頻寬下會造成較大的低通濾波器。如果我們欲降低此迴路濾波器的面積，可以利用一個除二電路來達到此目的。 | zh_TW |
| dc.description.abstract | Today System-on-Chip (SoC) is a mainstream for integrated-circuit design. PLLs are essential for SoC. The transistor size becomes much smaller when the CMOS process is improved, but not for on-chip passive components. A low-pass filter which is composed of capacitors and resistors is one of the building blocks in PLL. In the past years, a low-pass filter is always designed off-chip to reduce the chip size and production cost. Nowadays, a low-pass filter integrated into a chip is preferred for SoC. However, these passive components will occupy large area in a chip. We usually use a smaller bandwidth in a spread spectrum clock generator (SSCG), thus it will lead to a larger low-pass filter in the SSCG system. Since we want to reduce these passive components, a novel divided-by-two circuit is proposed and used in the PLL. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:13:30Z (GMT). No. of bitstreams: 1 ntu-95-R93943117-1.pdf: 3721115 bytes, checksum: b55e081058e93d8e38c50d9902d9e5d1 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | ABSTRACT ........................................................................................................i
LIST OF FIGURES .......................................................................................................v LIST OF TABLES ....................................................................................................viii CHAPTER 1 INTRODUCTION........................................................................1 1.1 Motivation.....................................................................................................1 1.2 Thesis Organization.......................................................................................3 CHAPTER 2 BASIC OF PHASE LOCKED LOOP..........................................5 2.1 Building Blocks.............................................................................................5 2.1.1 Voltage Controlled Oscillator............................................................5 2.1.2 Phase Frequency Detector..................................................................6 2.1.3 Charge Pump......................................................................................9 2.1.4 Loop Filter.......................................................................................11 2.2 Phase Noise Performance Analysis.............................................................14 2.2.1 Noise at Input...................................................................................14 2.2.2 Noise of VCO..................................................................................15 2.3 Charge-Pump PLL Design..........................................................................17 2.3.1 Second-Order PLL...........................................................................17 2.3.2 Third-Order PLL..............................................................................20 2.3.3 Fourth-Order PLL............................................................................23 CHAPTER 3 BASIC OF SPREAD SPECTRUM CLOCK GENERATION...27 3.1 Spread Spectrum Clocking Fundamental Theory........................................27 3.2 Spread Spectrum Modes and Amounts........................................................29 3.3 Modulation Frequency.................................................................................30 3.4 Modulation Profile.......................................................................................30 3.5 Implementation of SSCG............................................................................31 iv 3.6 Timing Impacts of Spread Spectrum Clock.................................................32 3.6.1 Cycle-to-Cycle Jitter........................................................................33 3.6.2 Long-Term Jitter..............................................................................34 CHAPTER 4 DESIGN OF SPREAD SPECTRUM CLOCK GENERATOR..37 4.1 System Architecture.....................................................................................37 4.2 Voltage Controlled Oscillator......................................................................38 4.3 Phase/Frequency Detector...........................................................................41 4.4 Charge Pump...............................................................................................41 4.5 Programmable Charge Pump.......................................................................42 4.6 Loop Filter...................................................................................................43 4.7 Divided-by-Two Circuit..............................................................................45 4.8 Modular Programmable Prescaler...............................................................46 CHAPTER 5 SIMULATION RESULT OF SPREAD SPECTRUM CLOCK GENERATOR……………………......................................................................49 5.1 SSCG Behavior Simulation.........................................................................49 5.2 Circuit Level Simulation.............................................................................51 5.2.1 Simulation Results of Voltage Controlled Oscillator.......................51 5.2.2 Phase/Frequency Detector and Charge Pump..................................53 5.2.3 Frequency Divider...........................................................................55 5.2.4 Closed-Simulation of Spread Spectrum Clock Generator...............57 CHAPTER 6 CONCLUSION...........................................................................64 REFERENCE .....................................................................................................66 | |
| dc.language.iso | en | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 展頻時脈 | zh_TW |
| dc.subject | phase lock loop | en |
| dc.subject | spread spectrum clock | en |
| dc.title | 展頻時脈產生器之設計與實作 | zh_TW |
| dc.title | Design and implementation of spread spectrum clock generator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成,林宗賢,遊竹,張棋 | |
| dc.subject.keyword | 展頻時脈,鎖相迴路, | zh_TW |
| dc.subject.keyword | spread spectrum clock,phase lock loop, | en |
| dc.relation.page | 66 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-95-1.pdf 未授權公開取用 | 3.63 MB | Adobe PDF |
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