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標題: | 矽鍺功率放大器設計與應變矽元件雜訊分析 SiGe Power Amplifier Design and Strained-Si Device Noise Analysis |
作者: | Wei-Chun Hua 華偉君 |
指導教授: | 劉致為(Chee Wee Liu) |
關鍵字: | 矽鍺,功率放大器,應變矽,閃爍雜訊,低雜訊放大器,封裝應力, SiGe,Power Amplifier,Strained Si,flicker noise,Low Noise Amplifier,Package Strain, |
出版年 : | 2006 |
學位: | 博士 |
摘要: | 本論文中,主要專注於IEEE 802.11b/g/n功率放大器設計,n型應變矽金氧半場效電晶體低頻雜訊特性分析,以及利用外加包裝應力的方式來降低低雜訊放大器電路的高頻雜訊指數。
首先,我們使用矽鍺異質接面雙載子電晶體設計出一個操作在IEEE 802.11b/g系統的功率放大器並具有高線性度且對溫度變化不敏感的特性。由於線性化偏壓的關係,1 dB增益壓縮點僅比飽合輸出功率低0.5 dB,此為目前我們所知的最佳紀錄。由於偏壓電路對溫度變化不敏感的特性,在IEEE 802.11b/g的線性輸出功率(24/20 dBm)下的總電流變化量小於 6% 與 10%。(0 ~ 85度範圍內,與25度的電流做比較)。此外,整合在晶片上的功率偵測器具有很高的動態範圍(20 dB)。藉由動態電流偏壓的方式,可以把直流偏壓降至53 mA, 並可在符合IEEE 802.11g線性度規範的前提下,將低輸出功率時的效率增加三倍。 接著我們以之前的IEEE 802.11b/g功率放大器為藍圖,在同一個晶片上設計一個應用於IEEE 802.11n標準,多收發器系統的矽鍺雙功率放大器,並提出前所未見的耦合效應研究。我們同時在元件以及電路層級上使用深溝隔絕與接地保護環來隔絕耦合效應,可以將兩個功率放大器之間的等效的小訊號耦合量降至 -30 dB。此功率放大器可以在單顆與雙顆操作模式下分別輸出18.1 dBm/16.6 dBm,並符合 IEEE 802.11g的線性度規範。功率放大器的誤差向量絕對值會因為另一顆功率放大器的干擾而變差,且干擾越大會越嚴重。 另外,我們提出高溫氧化層製備方式會對n型應變矽金氧半場效電晶體的低頻雜訊特性造成影響。高溫氧化層製備過程中,原本在矽/氧化層介面的空隙矽會注入到下方的矽/矽鍺介面,進而增強鍺外擴散到矽/氧化層介面而形成介面缺陷,並增加應變矽金氧半場效電晶體的低頻雜訊。鍺外擴散的問題可藉由低溫沉積氧化層的方式來解決。 接著,我們利用不同面積的n型應變矽金氧半場效電晶體來研究其線狀錯位對低頻雜訊特性的影響。以改良的載子波動模型加上因 Poison 分佈的線狀錯位所增加的缺陷,可以成功解釋與面積相關的低頻雜訊升高比例。每個線狀錯位可等效成 85 個缺陷,會使面積為 625 µm2 的元件,低頻雜訊增加約 4.2 倍。 經由實驗證實,n型應變矽金氧半場效電晶體的低頻雜訊與應變矽薄膜的厚度並無關聯,但會因為通道參雜上升而有些微增加。因此我們可以使用較厚的應變矽層以得到較高的電子遷移率,並同時不影響其低頻雜訊。 最後,我們同時以實驗以及理論計算的方式來證明經由外加包裝應力的方式可以降低低雜訊放大器電路的雜訊指數。雜訊指數降低主要原因是因為加上應力以後,電晶體遷移率增加的關係,應變矽元件的轉導與截止頻率也同時增加了。在0.037%的雙軸向拉伸應變下,雜訊指數可以在 2.4 GHz降低 0.53 dB (13%)。 In this dissertation, the power amplifiers (PAs) for IEEE 802.11b/g/n wireless local area networks applications are demonstrated and the high/low frequency noise characteristics of the strained-Si nMOSFETs are studied. A high-linearity and temperature-insensitive IEEE 802.11b/g PA with dynamic current bias is realized in a SiGe HBT technology with 0.9 µm emitter width. Due to the bias linearization, the P1dB of 27 dBm is only 0.5 dB smaller than Psat, which is the record low to the best of our knowledge. With simple temperature-insensitive bias, the total current deviations from the room temperature are smaller than 6% and 10% at the linear Pout (24/20 dBm) for IEEE 802.11b and IEEE 802.11g standards, respectively at the test temperature from 0 oC to 85 oC. The integrated power detector has a wide dynamic range of 20 dB. The dc current can be reduced to 53 mA and the power-added-efficiency (PAE) can be enhanced up to 3 times at low Pout level under dynamic current bias, and meanwhile the IEEE 802.11g linearity requirements are achieved. A dual SiGe PAs on a single chip is then implemented based on the platform of the previous IEEE 802.11b/g PA. The large-signal and small-signal coupling effects of dual SiGe PAs for IEEE 802.11n Multiple Input Multiple Output (MIMO) applications are demonstrated for the first time. Deep trench isolation and grounded guard ring are used for crosstalk isolation at both transistor and circuit levels. The equivalent small-signal coupling at 2.45 GHz between two PAs is -30 dB. The PA delivers 18.1 dBm and 16.6 dBm with 3% EVM (OFDM, 64-QAM) in single and dual PA operation modes, respectively. The EVM degradation becomes severe as the relative interfering power level increases. The flicker noise characteristics of strained-Si NMOSFETs are significantly dependent on the gate oxide formation. At the high temperature (900 oC) thermal oxidation, the Si interstitials at Si/oxide interface were injected into the underneath Si/SiGe heterojunction, and enhances the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si NMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700 oC) tetraethylorthosilicate (TEOS) gate oxide. The correlations between the threading dislocations and the low frequency noise characteristics of the strained-Si nMOSFETs are studied using the devices with different sizes. The device-area-dependent SVG (power spectral density of the gate referred voltage noise) ratio of the strained-Si devices over the control Si devices obtained form geometric average can be understood by the modified carrier number fluctuation model with excess traps from the Poisson distributed threading dislocations. The equivalent trap number per threading dislocation extracted from the area-dependent SVG ratios is ~85 for the strained-Si devices, and which results in about 4.2 times degradation of the SVG for the strained-Si device with the device area of 625 µm2. The low frequency noise of the strained-Si device also shows no strained-Si layer-thickness dependence and slightly depends on the channel impurity concentration. The strained-Si layer thickness independent low frequency noise implies that we can gain the benefit of higher mobility of the thicker strained-Si layer device without sacrificing the low frequency noise performance. The package strain improves the noise figure (NF) of the low noise amplifier (LNA). The maximum noise reduction is ~0.53 dB (13%) at the operating frequency of 2.4 GHz under the biaxial tensile strain of 0.037%. The NF reduction of the strained-LNA is mainly due to the enhanced transconductance and cut-off frequency of the individual nMOSFET device under the same strain and bias conditions. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23972 |
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顯示於系所單位: | 電子工程學研究所 |
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