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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23936完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為(Cheewee Liu) | |
| dc.contributor.author | Hsien-Ta Wu | en |
| dc.contributor.author | 吳賢達 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:12:45Z | - |
| dc.date.copyright | 2006-07-21 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-17 | |
| dc.identifier.citation | Chapter 2
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Kwong, “N-type Schottky barrier source/drain MOSFET using ytterbium silicide,” IEEE Electron Device Lett., vol. 25, pp. 565–567, June 2004. [10]S.M. Sze “Physics of semiconductor devices 2nd Edition” [11]Vincent W. L. Chin and John W. V. Storey “Characteristics of P-type PtSi Schottky diodes under reverse bias” J. Appl. Phys. 68(8), 15 Oct 1990 Chapter 4 [1] “Front end processes,” in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003. [2] G. Eftekhari Phys. Stat. sol (a) 161, 571 (1997) [3] C. Ren, et al., IEEE Electron Dev. Lett., Vol. 25, 124(2004) [4] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” Wiley Classics Library Edition Published 2003 [5] Dennis W. Scott et al “Low-resistance n-type polycrystalline InAs grown by molecular beam epitaxy” Journal of Crystal Growth 267 (2004) 35–41. [6] Oliver Dier et al “Selective and non-selective wet-chemical etchants for GaSb-based materials” Semicond. Sci. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23936 | - |
| dc.description.abstract | 本文中將介紹如何利用單光罩製程以製作蕭基汲/源極在矽鍺矽異質接面基板之電晶體，其中鉭上鍍鉑具有可靠抗BOE的特性，故使用其做為電晶體之金屬閘極。蕭基元件具有低電阻率、低溫製程及自動地形成不連貫的接面在金屬矽化物與矽之界面的性質，實驗中使用鉑鍍於n型基板而形成蕭基接面二極體元件作為源、汲極，在蕭基場效電晶體之特性中，異質接面基板的元件漏電流會比矽基板的元件大。此外，利用單光罩製程所製作元之蕭基電晶體都有嚴重的串聯電阻效應。蕭基極接面二極體在矽、鍺及矽鍺矽基板之元件特性也會被提出來討論，其中矽鍺矽基板之蕭基元件有獨特的電子特性，由電流電壓與電容電壓特性曲線圖可看出因異質接面而形成的電洞位能井會在逆偏壓時儲存電洞，而矽與鍺之蕭基二極體並看不到此現象。另外，將多晶三五族材料作為閘極金屬以利用其不同於多晶矽之能帶進而達到控制金氧半場效電晶體之門檻電壓的效果，最後，會聚焦於多晶砷化銦閘極之金氧半電容元件之特性，並改變摻雜元素以調整其佛米能階，在實驗中發現多晶砷化銦之功函數與理論值並不相符但改變參雜元素還是可以調控其功函數，亦發現成長多晶砷化銦的同時會造成氧化矽與矽基板界面之缺陷增加。 | zh_TW |
| dc.description.abstract | In this work, we focused on how to fabricate a schottky barrier source/drain (S/D) on Si/Ge/Si heterojunction substrate transistor by one mask process. Tantalum covered with Platinum would not be etched by BOE, so it is used to be the gate metal. Metal S/D SB device has some properties including low parasitic S/D resistance, low-temperature processing for S/D formation and atomically abrupt junctions formed at the silicide-silicon interface. In this experiment, the S/D of the transistor were made with platinum on n-type substrate schottky contact. In the characteristics of SB MOSFET, the device with Si/Ge/Si heterojunction substrate has larger leakage current than silicon substrate device. Then, the series resistance effect is serious on each SB MOSFET with one mask process. The schottky diodes with Si, Ge, and Si/Ge/Si (epi-Ge) substrate were also discussed. The schottky barrier diode with epi-Ge substrate has special electronic properties among them. The current-voltage and capacitance-voltage characteristic curves show that energy well in valance band which is due to different band gap of heterojunctions would confine holes at reverse bias, but it would not occur on PtSi and PtGe schottky diodes. Besides, using polycrystalline III-V materials which has different band gap with polycrystalline silicon controls threshold voltage of MOSFET. Finally, we concentrated on the characteristics of MOS capacitor with poly-InAs gate. The work function of poly-InAs did not match the theoretical value in this experiment, but it still could be tuned by changing the dopant elements. Interface trap density between silicon dioxide and silicon increased during growth of poly-InAs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:12:45Z (GMT). No. of bitstreams: 1 ntu-95-R93943144-1.pdf: 1292174 bytes, checksum: 8143703862dbb48f41573ba53f4a2d90 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Contents
List of Figures Ⅲ Chapter 1 Introduction 1.1 Motivation 1 1.2 Organization 2 Chapter 2 SB MOSFET Fabrication by One Mask Process 2.1 Introduction 4 2.2 Experiments 6 2.2.1 Substrate Fabracation 8 2.2.2 Lithography 11 2.2.3 Metal Lift Off 16 2.2.4 Oxide Etching 18 2.2.5 Source/Drain Metal Depositon 20 2.3 Results & Discussion 21 2.3.1 SB pMOSFET Fabricated on Si Substrate 21 2.3.2 SB pMOSFET Fabricated on Si/Ge/Si Substrate 23 2.4 Conclusions 28 References 28 Chapter 3 Metal semiconductor Schottky contact 3.1 Introduction 31 3.2 Basic Theory of Schottky Barrier Diode 32 3.2.1 Barrier Height 32 3.2.2 Depletion Layer 33 3.2.3 Ideality Factor 35 3.3 Experiments 35 3.4 Results & Discussion 37 3.3.1 I-V characteristics 37 3.3.2 C-V characteristics 39 3.4 Conclusions 41 References 42 Chapter 4 The Electrical characteristics of Poly-InAs MOS Capacitor 4.1 Introduction 45 4.2 Experiments 47 4.2.1 Growth of Poly-InAs by MBE 47 4.2.2 Experiment Procedure 47 4.3 Calculation of MOS capacitor 50 4.3.1 Interface Trap Density 50 4.3.2 Flat Band Voltage 53 4.4 Results & Discussion 54 4.4.1 200nm Poly-InAs Gate 54 4.4.2 1um Poly-InAs Gate 59 4.5 Conclusions 63 References 64 Chapter 5 Summary & Future Work 5.1 Summary 65 5.2 Future Work 65 | |
| dc.language.iso | en | |
| dc.subject | 三五族 | zh_TW |
| dc.subject | 蕭基場效電晶體 | zh_TW |
| dc.subject | Schottky barrier | en |
| dc.subject | poly III-V | en |
| dc.title | 蕭基場效電晶體製程與多晶III-V族閘極元件 | zh_TW |
| dc.title | Schottky barrier MOSFET process and poly III-V gate device | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張書通(Shu-Tong Chang),陳敏璋(Miin-Jang Chen),張廖貴術(Kuei-Shu Chang-Liao),蔡豐羽(Feng-Yu Tsai) | |
| dc.subject.keyword | 蕭基場效電晶體,三五族, | zh_TW |
| dc.subject.keyword | Schottky barrier,poly III-V, | en |
| dc.relation.page | 66 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-07-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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