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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑 | |
dc.contributor.author | Chung-Chieh Lee | en |
dc.contributor.author | 李中傑 | zh_TW |
dc.date.accessioned | 2021-06-08T05:12:43Z | - |
dc.date.copyright | 2006-07-20 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-17 | |
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Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,”IEEE Journal of Solid-State Circuits,vol: 36 ,pp.896-909, June 2001. [43] Lin Jia, Jian-GuoMa, KiatSengYeoand ManhAnhDo, “9.3-10.4-GHz-Band Cross-Coupled Complementary Oscillator with Low Phase-Noise Performance,”IEEE Trans. Microwave Theory and Techniques.,vol: 52 ,pp.1273-1278 , April 2004. [44] Young-Mi Lee and Ju-Sang Lee, “A 1.8-V Frequency Synthesizer for WCDMA in 0.18μm CMOS Process,”in Proc of IEEE. Midwest SymposiumonCircuits and Systems, 2002. pp.613-616, Aug. 2002. [45] Roberto Aparicioand Ali Hajimiri, “A Noise-Shifting Differential ColpittsVCO,”IEEE J. Solid-State Circuits, pp.1728 -1736, vol. 37, Dec. 2002 [46] Woogeun Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops”, Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on, vol. 2, pp. 545–548, 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23934 | - |
dc.description.abstract | 這幾年以來,無線通訊的發展日新月異,無線通訊無疑是未來的科技趨勢,為了因應市場需要,各種通訊協定紛紛制定,像是IEEE 802.11b,UWB,WiMAX,IEEE 802.11n等等。其中,IEEE 802.11a無線通訊協定選用國家通訊公用(UNII)的頻帶(5.15GHz ~ 5.35GHz,5.725GHz ~ 5.825GHz)來進行傳輸,並採用正交分頻多工調變(OFDM),此頻帶可以提供高速的資料傳輸(54Mbp),使得此協定和在2.4GHz頻帶的通訊協定(802.11b/g)相比下,能吸引更多無線通訊鏈結以此協定作產品實現。
在無線接收機的電路中,常利用鎖相迴路(phase-locked loop,PLL)的機制把接收到的信號和時脈作同步,才能進一步將訊號利用分析。而將鎖相迴路此種機制應用在無線收發機中,稱為頻率合成器,或是本地震盪器。頻率合成器在射頻電路中是一不可或缺的要件,設計一個兼具快速鎖定時間,低相位雜訊和高頻率解析度的頻率合成器也是許多論文在探討的問題。 802.11a的訊號動態範圍很大以及傳輸頻寬很寬,若將系統中的頻率合成器整合進入晶片之內,在相位雜訊(phase noise)和參考頻雜訊(reference noise)都將會面臨嚴苛的挑戰。為了涵蓋IEEE 802.11a如此寬的工作範圍,以及因元件製程與溫度上的變異,鎖相迴路中的壓控振盪器(voltage-controlled oscillator, VCO)將會是此系統關鍵。通常希望壓控振盪器具有很低的增益(Kvco),雖然許多文獻上有討論如何使壓控振盪器不具高增益,然而它們仍無法在如此高的操作頻率上,同時達到高頻寬與低雜訊敏感度。壓控振盪器本身幾乎決定了頻率合成器的相位雜訊,也決定了頻率合成器的輸出頻率,因此設計一良好的壓控振盪器是十分重要的一環。 本論文設計了應用於IEEE 802.11a通訊協定的頻率合成器,利用MASH 1-1-1的三角積分調變器改善頻率合成器輸出相位雜訊的影響,另外由積體電路實現一除小數之頻率合成器,利用三角積分調變作為除頻器之調變,藉由打亂除頻器模數,將傳統除小數頻率合成器所產生的小數突波(fractional spur)推至高頻,再經由鎖相迴路濾除。在此使用0.18μm CMOS製程,除了成本考量外,另一方面是因為CMOS在未來的系統中具有高度的整合效果。 | zh_TW |
dc.description.abstract | Nowadays, local oscillator is an essential component of the RF front-end. For market need, many kinds of wireless protocols have been setup, like IEEE 802.11b, UWB, WiMAX, IEEE 802.11n, etc. IEEE 802.11a is one of them using UNII band (5.15GHz ~ 5.35GHz,5.725GHz ~ 5.825GHz) and by OFDM to transmit data. This band allows high speed data communications (54Mbs), so becomes more attractive and fascinates more realization of wireless link and mobile communication, compared to the 2.4GHz (802.11b/g) counterpart.
In wireless transceiver design, we often use a phase-locked loop (PLL) circuit to synchronize the receiving signal and the receiving clock and then to analyze the signal. The PLL circuit used in wireless transceiver is called frequency synthesizer, or local oscillator. Frequency synthesizer is a very important component of RF circuit. And the design of a frequency synthesizer with agile settling speed, low phase noise and high frequency resolution has become a challenge. It has been well acknowledged that integration of an RF frequency synthesizer into a transceiver poses great challenge because the large dynamic range of the input signal and wide channel bandwidths have set stringent requirements for the synthesizer phase noise and spurious sideband levels. To cover such a wide tuning range and overcome the temperature and process variation, the voltage-controlled oscillator in a frequency synthesizer is the key point. Usually we need a low gain of VCO (KVCO). While techniques to avoid large KVCO have been developed, the characteristics of wide range and low sensitivity still cannot be realize concurrently in that high frequency of 5GHz. Voltage-controlled oscillator almost dominates the phase noise of a frequency synthesizer and determines the output frequency of frequency synthesizer. So it is the key point to design a good VCO. This Thesis discusses the influence of the MASH Sigma-Delta Modulator (SDM) to the synthesizer output phase noise. The integrated fractional-N frequency synthesizer is implemented with a MASH 1-1-1 SDM. On one hand, better fractional and reference spurious suppression are achieved by randomizing the modulus of frequency dividers; on the other hand, the spurious noise can be pushed to a higher frequency and will be further filtered out by the PLL. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:12:43Z (GMT). No. of bitstreams: 1 ntu-95-R93943077-1.pdf: 4903129 bytes, checksum: 30f2c214fe670b64711ed8eb3b5e805a (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v CHAPTER 1 INTRODUCTION 1 1.1 Motivation 2 1.2 Various Types of Frequency Synthesizer Architectures 3 1.2.1 Digital Synthesizer 3 1.2.2 Direct Synthesizer 4 1.2.3 PLL-Based Synthesizer 5 A. Integer-N Synthesizer 6 B. Fractional-N Synthesizer 7 C. Multi-Modulus Fractional-N Frequency Synthesizer 9 D. Multi-Phase Fractional-N Frequency Synthesizer 10 1.3 Fractional-N Synthesis in Various Communication Systems 10 1.4 IEEE 802.11b vs. IEEE 802.11a and Bluetooth 12 1.4.1 IEEE 802.11b 12 1.4.2 IEEE 802.11a 12 1.4.3 Bluetooth 13 1.5 Thesis Organization 13 CHAPTER 2 BASICS OF FREQUENCY SYNTHESIZER 15 2.1 General Considerations 16 2.1.1 Phase Noise 16 2.1.2 Spurs 18 2.2 Phase-Locked Loop Fundamentals 19 2.2.1 Voltage-Controlled Oscillator 20 2.2.2 Phase Frequency Detector 21 2.2.3 Charge Pump 24 2.2.4 Loop Filter 26 2.3 Phase Noise Performance Analysis 29 2.3.1 Noise at Input 29 2.3.2 Noise of VCO 31 2.4 Charge-Pump PLL Design 32 2.4.1 Second-Order PLL 32 2.4.2 Third-Order PLL 35 2.4.3 Fourth-Order PLL 39 CHAPTER 3 SYNTHESIZER ARCHITECTURE BEHAVIORAL SIMULATION …………………………………………………………………………………..43 3.1 Architecture 43 3.2 Frequency Planning 44 3.3 Design Considerations 45 3.4 Synthesizer Architecture 46 3.5 Behavioral Simulation 47 3.5.1 Integer-N PLL Model 49 3.5.2 Fractional-N PLL Model 51 CHAPTER 4 FREQUENCY SYNTHESIZER DESIGN 55 4.1 PLL Building Blocks 55 4.1.1 Phase Frequency Detector and Charge Pump 55 4.1.2 Loop Filter 59 A. Loop Filter Topology and Order 59 B. Phase Margin 59 C. Loop Bandwidth 59 4.1.3 Voltage Controlled Oscillator 62 A. Inductor 64 B. Switched-Cap Array 66 C. Four-Bit Switching Voltage Controlled Oscillator Core 71 4.1.4 Sigma Delta Modulator 72 A. Modulator Topology 73 B. Implementation of Pipelined MASH 1-1-1 Modulator 76 C. Accumulator Circuit 77 D. Noise Cancellation Network 79 4.1.5 Multi-Modulus Divider 82 4.1.6 Divided-By-Two Divider 84 A. Generating IQ Phase Divided-By-Two Divider 84 B. Decreasing VCO Output Frequency Divided-By-Two Divider 86 CHAPTER 5 SIMULATION AND MEAUREMENT RESULTS 87 5.1 Mixed Signal Design Flow 87 5.2 Simulation Results of PFD 88 5.3 Simulation Results of PFD and CP 90 5.4 Simulation Results of VCO 91 5.5 Simulation Results of MMD 94 5.6 Simulation Results of MASH 1-1-1 SDM 96 5.7 Simulation Results of Divided-By-Two Divider 98 5.8 Simulation Results of Closed-Loop 99 CHAPTER 6 CONCLUSION 103 REFERENCE 105 | |
dc.language.iso | en | |
dc.title | IEEE 802.11a頻率合成器之設計與實作 | zh_TW |
dc.title | Design and Implementation of a Frequency Synthesizer for IEEE 802.11a | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成,張棋,游竹 | |
dc.subject.keyword | 頻率合成器,802.11a, | zh_TW |
dc.subject.keyword | frequency synthesizer,802.11a, | en |
dc.relation.page | 109 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2006-07-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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