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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23475完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | Shuo-Wen Chang | en |
| dc.contributor.author | 張碩文 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:02:10Z | - |
| dc.date.copyright | 2011-08-22 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-19 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23475 | - |
| dc.description.abstract | 在本論文中，我們在台積電零點一八微米金氧半製程下，實現了兩個符合Zigbee應用規範的頻率合成器。其分別為整數型和分數型之頻率合成器，且操作頻率皆涵蓋2.4GHz~2.48GHz(Zigbee應用頻段)。Zigbee是一種類似藍芽的通訊協定，其具有低功率消耗、較慢傳輸速度需求、低成本等特色。電路實作的內容概要如下:
第一塊電路是一個符合Zigbee規格的整數型頻率合成器。為了降低其功率消耗，整塊電路都是操作於低電壓1.2伏特，並採用基極偏壓方法和短通道效應降低系統所需之操作最高電壓。從實驗結果可知，整顆頻率合成器只消耗12.62毫瓦。 第二塊電路為一個符合Zigbee規格的分數型頻率合器。和第一顆頻率合成器一樣皆操作在1.2伏特的低電壓。此電路使用三角積分調變器來實現分數型頻率合成器，因為它的分數突波較小，且其具有將量化雜訊移往高頻去的特性。另外，我們利用兩點調變的技巧，在壓控震盪器的輸入端加入一條具高通特性的調變路徑，減少頻率合成器跳頻鎖定所需的時間，進而降低整個無線收發器系統的功率消耗。由實驗結果可知，其鎖定時間減少為36微秒 最後，我們將根據實驗結果比較此兩顆頻率合成器的優劣，並作個總結。 | zh_TW |
| dc.description.abstract | An integer-N and a fractional-N frequency synthesizers for Zigbee standard are realized in TSMC 0.18-um process are presented in this thesis, and the frequency bands of the operation are also cover 2.4GHz~2.48GHz (Zigbee band). Zigbee is a wireless protocol which is similar to Bluetooth, and it has some features, such as low power, low data rate, and low cost. Two frequency synthesizers are introduced as follows:
The first chip is an integer-N frequency synthesizer for Zigbee standard. The whole system is operated at a low supply voltage 1.2-V in order to lower the power consumption. In addition, forward body-biasing technique and reverse short channel effect are used to lower the requirement of the supply voltage in the frequency synthesizers. According to the measurement results we can know the whole frequency synthesizer only consumes 12.62 mW. The second chip is a fractional-N frequency synthesizer for Zigbee standard. This frequency synthesizer is operated at a low supply voltage 1.2-V, which is the same as the first one chip. A delta-sigma modulator is adopted in this circuit to implement the fractional-N frequency synthesizer due to its lower spurs magnitude and high-pass noise shaping ability. In addition, a technique of the two-point channel control is used to add an additional high-pass control path to tune the VCO in order to reduce the PLL settling time. Furthermore, the power consumption of the wireless transceiver can be reduced. According to the measurement results we can know the PLL settling time is reduced to 36us. Finally, we compare advantages and shortcomings in these two frequency synthesizers according to the measurement results, and make a conclusion | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:02:10Z (GMT). No. of bitstreams: 1 ntu-100-R98943063-1.pdf: 4423802 bytes, checksum: 61588d3de893ea5e02be87ef7a1be078 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 誌謝 I
摘要 III ABSTRACT V CONTENTS VII List of figures X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Phase-Locked Loops 4 2.1 Basic Operation of the PLL 5 2.2 General Considerations 6 2.2.1 Phase Noise 6 2.2.2 Spurs 9 2.2.3 Lock Time 10 2.3 Building Blocks of Charge Pump PLL 11 2.3.1 Voltage-Controlled Oscillator (VCO) 11 2.3.2 Frequency Divider 14 2.3.3 Phase/Frequency Detector (PFD) 19 2.3.4 Charge Pump (CP) 22 2.3.5 Loop Filter 25 2.4 Analysis of the Loop System 26 2.4.1 Linear Transfer Function of the PLL 26 2.4.2 Linear Model of the PLL 27 Chapter 3 Fractional-N frequency Synthesizers 34 3.1 Introduction of the Integer-N/ Fractional-N Synthesis 35 3.1.1 Integer-N Frequency Synthesis 35 3.1.2 Fractional-N Frequency Synthesis 36 3.2 Quantization Noise 37 3.3 Delta-Sigma Modulator 39 Chapter 4 2.4GHz Integer/Fractional-N Frequency Synthesizers for Zigbee Standard 43 4.1 Introduction 43 4.2 Integer-N Frequency Synthesizer I 45 4.2.1 Architecture 45 4.2.2 LC-tank VCO with Switched-Capacitors Array 46 4.2.3 Truly Modular Divider with Division Ratio Extension 51 4.2.4 Switched-Mode Phase/Frequency Detector 59 4.2.5 Charge Pump with Forward Body-Biasing Technique 61 4.2.6 Third-Order Loop Filter 65 4.2.7 Quadrature Signal 66 4.3 Fractional-N Frequency Synthesizer II with Two-Point Channel Control 68 4.3.1 Introduction 68 4.3.2 Architecture 69 4.3.3 Reduced ΔΣ Modulator (DSM) 70 4.3.4 Auto-Frequency Calibration Loop (AFC) 72 4.3.5 Two-Point Channel Control for Fast Settling Performance 76 4.3.6 Digital-to-Analog Converter (DAC) 80 4.4 Measurement Results 82 4.4.1 Frequency Synthesizer I 82 4.4.2 Frequency Synthesizer II 91 4.4.3 Summary 99 Chapter 5 Conclusion 100 References…………………………………………………………………………….102 Appendix A PLL Measurements by SSA………………………………...………...106 Appendix B DCO for MICS Band………………………………..………………111 | |
| dc.language.iso | en | |
| dc.title | 適用於Zigbee系統之整數/分數型低功率頻率合成器 | zh_TW |
| dc.title | Integer-N and Fractional-N Low Power
Frequency Synthesizers for Zigbee System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,邱弘緯,陳筱青,汪濤 | |
| dc.subject.keyword | 頻率合成器,Zigbee,兩點調變技術,低功耗,鎖相迴路, | zh_TW |
| dc.subject.keyword | synthesizers,Zigbee,two-point channel control,low power,PLL, | en |
| dc.relation.page | 115 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2011-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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