請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23452
標題: | 用於減輕掃瞄鍊移位時電源供應雜訊峰值的測試時域最佳化 Test Clock Domain Optimization for Peak Power Supply Noise Reduction in Scan Shift Cycles |
作者: | Jen-Yang Wen 溫仁揚 |
指導教授: | 李建模(Chien-Mo Li) |
關鍵字: | 電源供應雜訊峰值,測試時域最佳化,可測試性設計,正反器密度, peak power supply noise,test clock domain optimization,design for testability,flip-flop density, |
出版年 : | 2010 |
學位: | 碩士 |
摘要: | 過度的電源供應雜訊造成的問題隨著製程技術進步越來越具挑戰。在掃瞄移位時脈邊緣時發生的電源供應雜訊峰值將導致掃瞄失效和良率損失。本論文提出了一個測試時域最佳化的可測試性設計來降低正反器密度,即掃瞄鍊位移時,一個區域內受同一測試時脈所觸發的正反器的最大數目。本技術只調整測試時域與掃瞄鍊的配置。自動測試圖樣產生的演算法和錯誤涵蓋率並未受到影響。在ITC'99中最大的電路b19上的實驗數據顯示,本技術成功的將傳統測試電電路上掃瞄鍊位移時的電源供應雜訊峰值降低了百分之四十九點二,而電路的面積只增加了百分之二。 Excessive power supply noise (PSN) is a more and more challenging problem when the design technology shrinks. The peak power supply noise (PPSN), which occurs at the clock edges of scan shift cycles, causes scan failure and yield loss. This thesis proposes a DfT technique called test clock domain optimization to reduce the PPSN during scan shift cycles by reducing the maximum flip-flop density (MFFD), which refers to the maximum number of flip-flops in triggered by the same test clock during scan shift cycles within a region. The proposed technique only adjusts the test clock domains and the scan chain configuration. The ATPG algorithm is not changed, and the fault coverage is preserved. The experimental data on the largest ITC’99 benchmark circuits b19 shows that the PPSN during the scan shift cycle is reduced 49.2% compared with the traditional technique while the area overhead is only 2%. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23452 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-99-1.pdf 目前未授權公開取用 | 997.71 kB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。