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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Wei-Ming Lin | en |
dc.contributor.author | 林韋名 | zh_TW |
dc.date.accessioned | 2021-06-08T05:00:09Z | - |
dc.date.copyright | 2010-08-20 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-08-17 | |
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Solid-State Circuits, vol. 39, no. 1, pp. 194-206, Jan. 2004. [21] T. Matano, Y. Takai, T. Takahashi, Y. Sakito, I. Fujii, Y. Takaishi, H. Fujisawa, S. Kubouchi, S. Narui, K. Arai, M. Morino, M. Nakamura, S. Miyatake, T. Sekiguchi and K. Koyama,“A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer,”IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 762-768, May 2003. [22] U. K. Moon,“CMOS high-frequency switched-capacitor filters for telecommunication applications,”IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 212-220, Feb. 2000. [23] S. Karthikeyan,“Clock duty cycle adjuster circuit for switched-capacitor circuits,”IEEE Electronics Letters, vol. 38, pp. 1008-1009, Aug. 2002. [24] G. Manganaro, S. U. Kwak and A. R. Bugeja,“A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer,”IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1829-1838, Nov. 2004. [25] http://www.auo.com/auoDEV/technology.php?sec=LTPS&ls=en [26] A. W. Wang and K. C. Saraswat,“A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors,”IEEE Trans. Electron Devices, vol. 47, no. 5, pp. 1035-1043, May 2000. [27] T. H. Lee, K. Donneily, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa,“2.5V delay-locked loop for an 18Mb 500MB/s DRAM,”in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1994, pp. 300-301. [28] T. Yoshimura, Y. Nakase, N. Watanabe, Y. Morooka, Y. Matsuda, M. Kumanoya, and H. Hamano,“A delay-locked loop and 90-degree phase shifter for 800Mbps double data rate memories,”in Symp. VLSI Circuits Dig. Papers, pp. 66-67, June 1998. [29] B. G. Kim and L. S. Kim,“A 250-MHz–2-GHz wide-range delay-locked loop,”IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, June 2005. [30] Y. J. Yoon, H. I. Kwon, J. D. Lee, B. G. Park, N. S. Kim, U. R. Cho, and H. G. Byun,“Synchronous mirror delay for multiphase locking,”IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 150-156, Jan. 2004. [31] A. Rossi and G. Fucili,“Nonredundant successive approximation register for A/D converters,”IEEE Electronics Letters, vol. 32, no. 12, pp. 1055-1057, June 1996. [32] G. K. Dehng, J. W. Lin, and S. I. Liu,“A fast-lock mixed-mode DLL using a 2-b SAR algorithm,”IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1464-1471, Oct. 2001. [33] K. Minami, M. Mizuno, H. Yamaguchi, T. Nakano, Y. Matsushima, Y. Sumi, T. Sato, H. Yamashida, M. Yamashina,“A 1GHz portable digital delay-locked loop with infinite phase capture ranges,”in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 350-351. [34] R. J. Yang and S. I. Liu,“A 40-550MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm,”IEEE J. Solid-State Circuits, vol. 42, no.2, pp. 361-373, Feb. 2007. [35] J. T. Kwak, C. Ki Kwon, K. W. Kim, S. H. Lee, J. S. Kih,“A low cost high performance register-controlled digital DLL for 1Gbps x32 DDR SDRAM,”in Symp. VLSI Circuits Dig. Papers, pp. 283-284, June 2003. [36] T. Hamamoto, K. Furutani, T. Kubo, S. Kawasaki, H. Iga, T. Kono, Y. Konishi and T. Yoshihara,“A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM,”IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 194-206, Jan. 2004. [37] Y. J. Jeon, J. H. Lee, H. C. Lee, K. W. Jin, K. S. Min, J. Y. Chung, and H. J. Park,“A 66–333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs,”IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2087-2092, Nov. 2004. [38] J. S. Wang, Y. M. Wang, C. H. Chen, Y. C. Liu,“An ultra-low-power fast-lock-in small-jitter all-digital DLL,”in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2005, pp. 422-423 and 607. [39] W. M. Lin and S. I. Liu,“An all-digital reused-SAR delay-locked loop with adjustable duty cycle,”in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 312-315. [40] F. Mu and C. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23379 | - |
dc.description.abstract | 隨著製程科技快速的演進,越來越多類比與數位電路被整合到單一晶片上,同步化的控制相對於非同步來說較為簡單且更常被採用,然而,時脈的特性通常會大幅地影響系統的效能,此時脈的產生通常由一個鎖相迴路或延遲鎖定迴路來實現,因此,設計一個鎖相迴路或延遲鎖定迴路來滿足特定的需求是相當重要的。首章介紹在鎖相迴路或延遲鎖定迴路中一些時脈的非理想現象與限制,主要針對五個主題:(1)充電泵電流不匹配;(2)錯誤鎖定與諧波鎖定;(3)時間放大;(4)相位雜訊;(5)時脈的責任周期。
第二章提出一個充電泵自我校正的鎖相迴路來改善充電泵的電流不匹配,與一個阻抗提升技巧來增加充電泵的輸出阻抗,此鎖相迴路以3um低溫多晶矽薄膜電晶體製程來實現,晶片面積為18.9mm^2,在8.4V的電源下,操作頻率從5.6MHz至10.5MHz,在10.5MHz下,功率消耗為7.81mW。 第三章提出一個以環型振盪器為基礎的相位誤差累積方法,並用在一個延遲鎖定迴路來解決充電泵電流不匹配,另外用一個類比相位偵測器來避免錯誤與諧波鎖定,此延遲鎖定迴路以CMOS 0.18um製程來實現,晶片面積為0.7mm^2,在1.8V的電源與750MHz的操作頻率下,功率消耗為16.2mW。 第四章實現一個以環型振盪器為基礎的高增益與高線性度時間放大器,並包括一個閉迴路增益控制。此時間放大器應用到一個鎖相迴路來降低頻寬內的相位雜訊,而第三章所提的充電泵校正技術也被用在這個鎖相迴路中。時間放大器與鎖相迴路皆以CMOS 0.18um製程來實現,時間放大器的晶片面積為0.438mm^2,在1.8V的電源與10MHz的操作頻率下,功率消耗為25.8mW。鎖相迴路的晶片面積為0.9801mm^2,在1.8V的電源與1GHz的操作頻率下,功率消耗為35.24mW。 第五章介紹一個全數位可調責任周期延遲鎖定迴路,主要討論時脈的責任周期與解決錯誤與諧波鎖定,此延遲鎖定迴路以CMOS 0.18um製程來實現,核心面積為0.054mm^2,在1.8V的電源與800MHz的操作頻率下,一個輸出時脈的功率消耗為2.7mW。此外,本章舉了一個二階三角積分調變器作為數位責任周期校正的例子,此調變器是以3um低溫多晶矽薄膜電晶體製程來實現,晶片面積為52.25mm^2,在11.2V的電源與350kHz的取樣頻率下,功率消耗為158mW。 最後,第六章針對本論文作總結並提出一些未來的研究方向。 | zh_TW |
dc.description.abstract | As the process technology is rapidly scaled down, more and more analog and digital circuits are integrated in a single chip. A synchronous control is simple and preferred compared with the asynchronous one. However, the characteristics of a clock usually influence the system performance substantially. This clock generation is usually realized by a phase-locked loop (PLL) or delay-locked loop (DLL). Therefore, to design a PLL or DLL to satisfy certain requirements is really important. The first chapter introduces some imperfections and limitations of the clock in a PLL or DLL. They focus on five topics: (1) current mismatch in charge pump; (2) false locking and harmonic locking; (3) time amplification; (4) phase noise; (5) duty cycle of a clock.
Chapter 2 proposed a PLL with self-calibrated charge pumps to improve the current mismatch in charge pump. And an impedance boosting technique is proposed to increase the output impedance of the charge pump. This PLL has been fabricated in a 3µm low-temperature poly-silicon thin-film transistor (LTPS-TFT) technology. It operates from 5.6MHz to 10.5MHz at a supply of 8.4V. Its area is 18.9mm^2 and consumes 7.81mW at 10.5MHz. In chapter 3, a ring-oscillator based phase error accumulation method is proposed and applied to a DLL for charge pump calibration. An analog phase detector is proposed to avoid the false and harmonic locking. This DLL has been fabricated in a CMOS 0.18µm technology. Its area is 0.7mm^2 and consumes 16.2mW at 750MHz from a supply of 1.8V. In chapter 4, a ring-oscillator based time amplifier is proposed to achieve the high-gain and high-linearity. And a closed-loop gain control is included. This time amplifier is applied to a PLL to reduce the in-band phase noise of the PLL. Besides, the charge pump calibration technique in chapter 3 is also adopted in this PLL. The TA and PLL have been simulated in a CMOS 0.18µm technology. The chip area of the TA is 0.438mm^2 and consumes 25.8mW at 10MHz from a supply of 1.8V. The chip area of the PLL is 0.9801mm^2 and consumes 35.24mW at 1GHz from a supply of 1.8V. Chapter 5 introduces an all-digital DLL with adjustable duty cycle. It discussed the duty cycle of a clock and solves the false and harmonic locking. This DLL has been fabricated in a CMOS 0.18µm technology. Its core area is 0.054mm^2 and consumes 2.7mW with one output clock at 800MHz from a supply of 1.8V. Besides, this chapter gives a second-order sigma-delta modulator (SDM) as an example about digital duty cycle calibration. This modulator has been fabricated in a 3µm LTPS-TFT technology. Its area is 52.25mm^2 and consumes 158mW at 350kHz sampling clock from a supply of 11.2V. Finally, chapter 6 gives the conclusion of this dissertation and some interesting research aspects for future work are described. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:00:09Z (GMT). No. of bitstreams: 1 ntu-99-D92943013-1.pdf: 13390121 bytes, checksum: 7e037dc3383b92b87897e10a38e0470b (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | 1. Introduction............................................1
1.1 Imperfections and Limitations of the Clock in PLL and DLL..................................................2 1.1.1 Current Mismatch in Charge Pump...................2 1.1.2 False Locking and Harmonic Locking................5 1.1.3 Time Amplification................................6 1.1.4 Phase Noise.......................................7 1.1.5 Duty Cycle of a Clock............................10 1.2 Organization........................................10 2. A Phase-Locked Loop with Self-Calibrated Charge Pumps in 3µm LTPS-TFT Technology................................13 2.1 Introduction........................................14 2.2 Circuit Description.................................15 2.3 Simulation and Experimental Results.................22 2.4 Summary.............................................29 2.5 Appendix 1-Curve Fitting...........................30 2.6 Appendix 2-Jitter and Spur Performance Estimation..31 3. A Delay-Locked Loop with Gated Ring Oscillator-Based Charge Pump Calibration................................33 3.1 Introduction........................................34 3.2 Circuit Description.................................35 3.3 Experimental Results................................47 3.4 Summary.............................................52 3.5 Appendix-Mismatch in Two GROs......................53 4. Design and Application of the Gated Ring Oscillator- Based High-Gain and High-Linearity Time Amplifier......55 4.1 Introduction........................................56 4.2 Principle of the Gated Ring Oscillator-Based Time Amplifier...........................................57 4.3 Application of the Time Amplifier in Phase-Locked Loop................................................62 4.4 Testing of the Stand-Alone Time Amplifier...........72 4.5 Summary.............................................78 5. An All-Digital Reused-SAR Delay-Locked Loop with Adjustable Duty Cycle..................................79 5.1 Introduction........................................80 5.2 Circuit Description.................................80 5.3 Experimental Results................................95 5.4 Summary............................................100 5.5 Example of Digital Duty Cycle Calibration..........101 5.5.1 Circuit Description.............................101 5.5.2 Experimental Results............................104 5.5.3 Summary.........................................108 6. Conclusion and Future Work............................109 6.1 Conclusion..........................................109 6.2 Future Work.........................................110 Bibliography.............................................113 Publication List.........................................119 | |
dc.language.iso | en | |
dc.title | 使用CMOS與LTPS製程設計與實現具有充電泵校正之時脈產生器 | zh_TW |
dc.title | Design and Implementation of Clock Generators with Charge Pump Calibration in CMOS/LTPS Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),楊清淵(Ching-Yuan Yang),郭泰豪(Tai-Haur Kuo),黃柏鈞(Po-Chiun Huang),陳巍仁(Wei-Zen Chen),吳介琮(Jieh-Tsorng Wu) | |
dc.subject.keyword | 互補式金氧半,低溫多晶矽,鎖相迴路,延遲鎖定迴路,充電泵, | zh_TW |
dc.subject.keyword | CMOS,LTPS,PLL,DLL,charge pump, | en |
dc.relation.page | 119 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2010-08-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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