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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為 | |
dc.contributor.author | Chao-Yun Lai | en |
dc.contributor.author | 賴昭昀 | zh_TW |
dc.date.accessioned | 2021-06-08T04:50:15Z | - |
dc.date.copyright | 2009-07-29 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-27 | |
dc.identifier.citation | References
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[7] Jeff Wu1, Xin Wang, “Stress Engineering for 32nm CMOS Technology Node,” Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, pp. 113-116, 2008. [8] T. Miyashita, T. Owada*, A. Hatada*, Y. Hayami, K. Ookoshi*, T. Mori*, H. Kurata, and T. Futatsugi, “Physical and Electrical Analysis of the Stress Memorization Technique (SMT) using Poly-Gates and its Optimization for Beyond 45-nm High-Performance Applications,” IEDM Tech. Dig., pp.1-4, 2008. [1] T. Guillaume, M. Mouis, S. Maîtrejean, A. Poncet, M. Vinet, and S. Deleonibus, “Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs,” in Proc. ESSDERC, 2004, pp. 393–396. [2] T. Komoda, A. Oishi, T. Sanuki, K. Kasai, H. Yoshimura, K. Ohno, M. Iwai, M. Saito, F.Matsuoka, N. Nagashima, and T. Noguchi, “Mobility improvement for 45 nm node by combination of optimized stress control and channel orientation design,” in IEDM Tech. Dig., 2004, pp. 217–220. [3] S. Pidin, T. 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[6] Kuo-Shen Chena, , Xin Zhangb, Shih-Yuan Lin, “Intrinsic stress generation and relaxation of plasma-enhanced chemical vapor deposited oxide during deposition and subsequent thermal cycling,” Thin Solid Films 434 (2003) 190–202 [7] Stéphane Orain, Vincent Fiori, Davy Villanueva, Alexandre Dray, and Claude Ortolland, “Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 4, APRIL 2007. [8] Ohta, H. Tamura, N. Fukutome, H. Tajima, M. Okabe, K. Hatada, A. Ikeda, K. Ohkoshi, K. Mori, T. Sukegawa, K. Satoh, S. Sugii, T., “High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster,” in IEDM Tech. Dig., 2007, pp. 289–292. [9] Jeff Wu1, Xin Wang, “Stress Engineering for 32nm CMOS Technology Node,” Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, pp. 113-116, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23259 | - |
dc.description.abstract | 利用電晶體的微縮來改善互補式金屬氧化層半導體場效電晶體的性能已經至少三十年了,由於元件的微縮已經幾乎達到了物理的極限,工業界與研究團體開始積極的找尋一些非傳統的解決方法。 其中藉由改變矽通道內的應變與應力來達到元件性能的改善,是一個已經廣泛被運用在現行製程技術中的解決方法。
接觸蝕刻停止層是其中一種應變與應力工程,自九十奈米的技術開始,接觸蝕刻停止層就開始被用來改善互補式金屬氧化層半導體場效電晶體的性能,而這個接觸蝕刻停止層是由氮化物所組成,原本是用於金屬接觸的蝕刻停止。 另一種應變與應力工程是應力記憶技術,這是少數對N型場效電晶體的性能可以改善的技術之一,而這項技術也是現今製程中不可或缺的技術之一,它不只用在傳統的多晶矽閘極,也用在金屬嵌入多晶矽閘極還有金屬閘極的技術中。有兩個主要的理論支持著應力記憶技術,一個是朔性變形模型,另一個是多晶矽閘極的體積膨脹。 最後,我們討論一些其他能改善元件性能的應力與應變的模擬,如接觸蝕刻停止層厚度對元件的影響,多晶矽閘極之間的距離對元件的影響,對本質應力成份的分解,參雜物限制層技術,多重的應力記憶技術,源極與汲極中的應力記億技術,絕緣暈用於防止淺溝渠隔離層的效應。 | zh_TW |
dc.description.abstract | Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. Approaching the fundamental limits of transistor scaling leads the industry and the research community to actively search for alternative solutions. The use of strained Si obtained by stress engineering seems to be one solution to achieve transistor performance improvements.
One of stress engineering is contact etch stop layer (CESL), since the 90nm CMOS technology node, the CESL is used as a stress-engineering booster that enables transistor improvement, and the CESL consists in a nitride layer used to stop the etching of the metallic contact. The other one of stress engineering is stress memorization technique (SMT), the SMT is one of the few strain techniques for N-FET performance enhancement, and it has been a necessary technique in recent high-performance technology not only for conventional poly-gates, but also for MIPS (Metal Inserted Poly-silicon Stack) and metal gates. There are two major theory support SMT, one is plastic deformation model and the other one is poly-gate volume expansion. Finally, other simulations for strain enhancement techniques are discussed. Such as the influence of CESL thickness and poly spacing, decomposition of the intrinsic stress, the Dopant Confinement Layer (DCL) technique, Multi-SMT, SMT in source and drain, the insulating halo for shallow trench isolation (STI). | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:50:15Z (GMT). No. of bitstreams: 1 ntu-98-R96943011-1.pdf: 4282283 bytes, checksum: 030fa9cc574727bf7abacda903ba7fae (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Contents
List of Figures VII Chapter 1 Introduction 1.1 Background and Motivation 1 1.2 Organization 2 1.3 Origin of stress 3 1.3.1 Epitaxial stress 3 1.3.2 Thermal stress 4 1.3.3 Intrinsic stress 5 1.4 The simulation tool 10 References 10 Chapter 2 The Strain and Stress Simulation of CESL (Contact Etch Stop Layer) 2.1 Introduction 13 2.2 Model Description 14 2.3 Assumptions 15 2.4 Long Channel device 17 2.5 Short channel device 19 2.6 Mechanism description 20 2.7 Direct effects 23 2.8 Indirect effects 29 2.9 Corner effect 34 2.10 Conclusion 42 References 42 Chapter 3 The Strain and Stress Simulation of SMT (Stress Memorization Technique) 3.1 Introduction 44 3.2 History of stress memorization technique 46 3.3 Poly-gate volume expansion 47 3.3.1 Mechanism description 47 3.3.2 Modeling poly-gate volume expansion 50 3.4 Plastic deformation model 54 3.4.1 Mechanism description 54 3.4.2 Model description 57 3.5 Simulation for SMT 59 3.5.1 Assumption 59 3.5.2 The simulation procedure 61 3.6 Conclusion 64 Reference 64 Chapter 4 Other Simulations for Strain enhancement technique 4.1 Introduction 67 4.2 Other effects of contact etch stop layer 67 4.2.1 The influence of CESL thickness 67 4.2.2 The influence of poly spacing 69 4.2.3 Decomposition of intrinsic stress 70 4.3 Other effects of stress memorization technique 74 4.3.1 Dopant Confinement Layer (DCL) technique as a Strain Booster 74 4.3.2 Multi-SMT 79 4.3.3 Stress memorization technique in source/drain 81 4.4 Insulating halo 85 4.5 Conclusion 89 Reference 90 Chapter 5 Summary and Future Work 5.1 Summary 92 5.2 Future Work 93 | |
dc.language.iso | en | |
dc.title | 45奈米以下之元件其應力與應變的模擬與分析 | zh_TW |
dc.title | The Strain and Stress Simulation for
45nm CMOS Technology Node and Beyond | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡銘進,陳其賢,汪大暉 | |
dc.subject.keyword | 接觸蝕刻停止層,應力記憶技術,朔性變形模型,多晶矽閘極的體積膨脹,參雜物限制層技術,絕緣暈,淺溝渠隔離層, | zh_TW |
dc.subject.keyword | CESL,SMT,plastic deformation model,poly-gate volume expansion,DCL,insulating halo,STI, | en |
dc.relation.page | 93 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-07-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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