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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維 | |
dc.contributor.author | Wei-Lun Lu | en |
dc.contributor.author | 呂維倫 | zh_TW |
dc.date.accessioned | 2021-06-08T04:42:37Z | - |
dc.date.copyright | 2009-08-20 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-06 | |
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[14] Young Jun Cho and Jae Wook Jeon. Design of an efficient initialization method of a log-based file system with flash memory. In Industrial Informatics, 2008. INDIN 2008. 6th IEEE International Conference on, pages 1620-1625, July 2008. [15] In Hwan Doh, Hyo J. Lee, Young Je Moon, Eunsam Kim, Jongmoo Choi, Donghee Lee, and Sam H. Noh. Impact of nvram write cache for file system metadata on i/o performance in embedded systems. In SAC '09: Proceedings of the 2009 ACM symposium on Applied Comput- ing, pages 1658- pages = 1658-1663, location = Honolulu, Hawaii, doi = http://doi.acm.org/10.1145/1529282.1529654, address = New York, NY, USA,, 2009. [16] DRAMeXchange. Flash Contract Price,http://www.dramexchange.com/, 03 2009. [17] Heeseung Jo, Jeong-Uk Kang, Seon-Yeong Park, Jin-Soo Kim, and Joonwon Lee. FAB: Flash-aware BuRer Management Policy for Portable Media Players. In IEEE Transactions on Consumer Electronics, pages 485-493. IEEE, 2006. [18] Sooyong Kang, Sungmin Park, Hoyoung Jung, Hyoki Shim, and Jaehyuk Cha. Performance trade-offs in using nvram write buffer for flash memory-based storage devices. Computers, IEEE Transactions on, 58(6):744-758, June 2009. [19] Atsuo Kawaguchi, Shingo Nishioka, and Hiroshi Motoda. A Flash-Memory Based File System. In the 1995 USENIX Technical Conference, pages 155-164, Jan 1995. [20] Hyojun Kim and Seongjun Ahn. BPLRU : A Buffer Management Scheme for Improving Random Writes in Flash Storage. In the 6th USENIX Conference on File and Storage Technologies (FAST), pages 239-252, 2008. [21] Seokhyun Kim and Yookun Cho. The design and implementation of flash cryptographic file system based on yaffs. In Information Science and Security, 2008. ICISS. International Conference on, pages 62-65, Jan. 2008. [22] Chul Lee, Sung Hoon Baek, and Kyu Ho Park. A hybrid flash file system based on nor and nand flash memories for embedded devices. IEEE Trans. Comput., 57(7):1002-1008, 2008. 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Storing a Persistent Transactional Object Heap on Flash Memory. In the 2006 ACM Conference on Language, Compilers, and Tool Support for Embedded Systems (LCTES), pages 22-33, 2006. [29] STMicroelectronics. NAND08Gx3C2A 8Gbit Multi-level NAND Flash Memory, 2005. [30] Yi-Lin Tsai, Jen-Wei Hsieh, and Tei-Wei Kuo. Configurable nand flash translation layer. In Sensor Networks, Ubiquitous, and Trustworthy Computing, 2006. IEEE International Conference on, volume 1, pages 8 pp.-, June 2006. [31] Chin-Hsien Wu and Tei-Wei Kuo. An Adaptive Two-level Mnagement for the Flash Translation Layer in Embedded Systems. In the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 601-606, 2006. [32] Chin-Hsien Wu, Tei-Wei Kuo, and Chia-Lin Yang. A space-efficient caching mechanism for flash-memory address translation. In Object and Component-Oriented Real-Time Distributed Computing, 2006. ISORC 2006. Ninth IEEE International Symposium on, pages 8 pp.-, April 2006. [33] Po-Liang Wu, Yuan-Hao Chang, and Tei-Wei Kuo. A File-System-Aware FTL Design for Flash-Memory Storage Systems. In the ACM/IEEE Design, Automation and Test in Europe (DATE), 2009. [34] Qin Xin, Ethan L. Miller, Thomas Schwarz, Darrell D.E. Long, Scott A. Brandt, and Witold Litwin. Reliability Mechanisms for Very Large Storage Systems. In the 20th IEEE / 11th NASA Goddard Conference on Mass Storage Systems and Technologies (MSS), pages 146-156, Apr 2003. [35] Seon yeong Park, Dawoon Jung, Jeong uk Kang, Jin soo Kim, and Joonwon Lee. CFLRU: a Replacement Algorithm for Flash Memory. In the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2006. [36] Keun Soo Yim, Hyokyung Bahn, and Kern Koh. A Flash Compression Layer for SmartMedia Card Systems. IEEE Transactions on Consumer Electronics, 50(1):192-197, Feburary 2004. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23114 | - |
dc.description.abstract | 在行動裝置上雖然固態硬碟已經成為傳統硬碟的優秀替代品,但是由於效能和可靠度的關注而產生了嚴重的挑戰。此論文目標為針對具有低成本多層單元快閃記憶體之限制的提升效能之設計。一個有效率的快閃記憶體管理之設計被提出以管理具有快取支援的多個晶片之快閃記憶體,並且一個兩層的位址轉譯機制搭配一個有適應能力的快取決策被提出。本提出方法之效能由一個基於實際工作量和衡量標準之SystemC為基礎的固態硬碟模擬器所評估。評估結果顯示了本提出方法能夠顯著地提升不同硬體架構之多晶片固態硬碟的效能。 | zh_TW |
dc.description.abstract | Although solid-state disks seem being excellent alternatives to replace hard disks in mobile devices, serious challenges arise due to performance and reliability concerns. This work targets performance enhancement designs with the considerations of low-cost MLC flash memory. In particular, an efficient flash management design is proposed to manage multi-chipped flash memory with cache support, where a two-level address translation mechanism is presented with an adaptive caching policy. The capability of the proposed approach is evaluated with a SystemC-based solid-state-drive simulator based on realistic workloads and benchmarks. It was shown that the proposed approach could significantly improve the performance of multi-chipped solid-state disks over various hardware configurations. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:42:37Z (GMT). No. of bitstreams: 1 ntu-98-R96922018-1.pdf: 799930 bytes, checksum: b2efc7d0233c804b21808fc8d1a75699 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Abstract ix
Contents xi List of Figures xiii List of Tables xv 1 Introduction 1 2 System Architecture and Research Motivation 5 2.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 A Multi-Chipped FTL with Caching Support 9 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 A Caching-Oriented Mapping Mechanism . . . . . . . . . . . . . . . . 11 3.2.1 Address Translation with Caching Support . . . . . . . . . . . 11 3.2.2 Heap-Like Index Structure . . . . . . . . . . . . . . . . . . . . 12 3.3 Access Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 An Adaptive Caching Policy . . . . . . . . . . . . . . . . . . . 14 3.3.2 Chain-Based Block Management . . . . . . . . . . . . . . . . . 16 3.3.3 Circular-Based Cleaner . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Implementation Remarks . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Conclusion 23 Bibliography 25 | |
dc.language.iso | en | |
dc.title | 多晶片固態硬碟之高效快閃記憶體轉譯層設計 | zh_TW |
dc.title | An Efficient FTL Design for Multi-Chipped Solid-State Disks | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳銘憲,施吉昇,逄愛君,張韻詩,黃佑充,謝錫? | |
dc.subject.keyword | 固態硬碟,快閃記憶體轉譯層, | zh_TW |
dc.subject.keyword | Solid-State Disk,FTL, | en |
dc.relation.page | 29 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-08-06 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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