在超高速且低供應電壓SDRAM I/O電路中使用去耦合電容對電源完整性及信號完整性的影響

Abstract

本論文闡述一個操作在1.1伏特傳輸速度為3.2Gb/s的DDR4 I/O介面傳輸電路，並以聯電90-nm CMOS製程製作。在此晶片中包含了傳輸器以及接收器電路，並加入了多組的去耦合電容以及傳輸器電路，用來探討電源完整性的議題。另外在文中也會考慮此傳輸接收器在不同的情況下所產生的眼圖及傳遞延遲時間，討論電路的信號完整性。 由於在本文中有探討關於不同製程、電壓、溫度的影響下且用不同的模型，其中包含晶片、晶片加上封裝、晶片加上封裝及電路板的模型所模擬出來的結果，發現在不同製程、電壓、溫度下電路的效能雖然會有影響，但其影響皆沒有我們加入了封裝及電路板的模型進行模擬後的差異來的大，由此可知在高速電路下封裝及電路板模型建立的重要性，因此在此高速電路下我們也針對了板子的特性進行了模型的建立來進行模擬，並在最後比較我們量測及模擬的結果。

This thesis presents a DDR4 I/O interface circuits operated at 1.1V and data rate is 3.2Gb/s. It is produced by standard UMC 90-nm CMOS process. In this chip, the transmitter and receiver circuits are included. To discuss the power integrity issue, we add many decoupling capacitors and transmitter circuits. In addition, we also consider transceiver’s eye-diagram and propagation delay time in different condition and discuss the signal integrity of this circuit. In this thesis, the variation of process, voltage and temperature with different model is discussed. It is included chip, chip with package and chip with package and board model which are simulated. And the result shows that although the performance is affected by the variation of process, voltage and temperature. But the effect by PVT is not more critical than we add the package and board model. Due to this reason, it is important to establish the package and board model in our simulation. Therefore, we also establish the board model which we measured and use it into our simulation. At the end, we compare with the result of our measurement and simulation.