請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23012
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑 | |
dc.contributor.author | Ssu-Wen Hung | en |
dc.contributor.author | 洪泗紋 | zh_TW |
dc.date.accessioned | 2021-06-08T04:37:43Z | - |
dc.date.copyright | 2009-08-21 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-17 | |
dc.identifier.citation | [1] S. Borkar, “Thousand Core Chips-A Technology Perspective,” in Proc. ACM/IEEE Design Automation Conf.(DAC), pp.746-749, Jun. 2007.
[2] A. Jantsch and H. Tenhunen (Eds.), Networks on Chip, Kluwer Academic Publishers, 2003. [3] W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 684-689, 2001. [4] L. Benini and G. De Micheli, “Networks on Chips: a New SoC paradigm,” IEEE Computer, vol. 35, no.1, pp.70-78, Jan. 2002. [5] E. S. H. Hou, N. Ansari, and H. Ren, “A Genetic Algorithm for Multiprocessor Scheduling,” IEEE Trans. on Parallel and Distributed Systems, vol. 5, no. 2, pp. 113-120, Feb. 1994 [6] C. M. Krishna and K. G. Shin, Real-time Systems, WCB/McGraw Hill, 1997. [7] H. El-Rewini, H.H.Ali and T.Lewis, “Task Scheduling in Multiprocessor Systems,” IEEE Computer, vol. 28, no. 12, pp. 27-37, Dec. 1995. [8] T. Burd and R. W. Brodersen, “Energy efficient CMOS microprocessor design,” in Proc. Hawaii International Conference on System Sciences(HICSS), pp. 288-297, Jan. 1995. [9] G. quan and X. Hu, “Energy efficient fixed-priority scheduling for real-time systems on voltage variable processors,” in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 828-833, Jun. 2001. [10] M. T. Schmitz and B. M. Al-Hashimi, “considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems,” in Proceedings International Symposium System Synthesis(ISSS), pp. 250-255, Oct. 2001. [11] M. T. Schmitz, B. M. Al-Hashimi, and P. Eles, “Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems,” in Proc. Design, Automation and Test in Europe Conf. (DATE), pp 514-521, Mar. 2002. [12] M. T. Schmitz and B. M. Al-Hashimi, and P. Eles, “Iterative Schedule Optimization for Voltage Scalable Distributed Embedded Systems,” ACM Trans. Embedded Comput. Syst. (TECS), vol. 3, no. 1, pp. 182-217, Feb. 2004. [13] V. Kianzad, et al., “CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems,” in Proceedings of Application-specific Systems, Architectures and Processors(ASAP), pp. 191-197, Jul. 2005. [14] P. Chang, et al., “ETAHM: An Energy-Aware Task Allocation Algorithm for Heterogeneous Multiprocessor,” in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 776-779 Jun. 2008. [15] Y. Zhang, X. Hu, and D. Z. Chen, “Task Scheduling and Voltage Selection for Energy Minimization,” in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 183-188 , Jun. 2002. [16] G. Varatkar and R. Marculescu, “Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization,” in Proc. Intl. Conf. on Computer-Aided Design (ICCAD), pp. 510-517, Nov. 2003. [17] J. Hu and R. Marculescu, “Energy-Aware Communication and Task Scheduling for Network-on-Chip Architetures under Real-Time Constraints,” in Proc. Design, Automation and Test in Europe Conf. (DATE), pp. 234-239, Feb. 2004. [18] T. Ishihara and H. Yasuura, “Voltage Scheduling Problem for Dynamically Variable Voltage Processors,” in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 197-202, Aug. 1998. [19] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, San Francisco: W. H Freeman, 1979. [20] M. Bomze et al., The Maximum Clique Problem, in Handbook of Combinatorial Optimization, vol. 4, D.-Z. Du and P. M. Pardalos, editors, Kluwer Academic Publishers, Boston, MA, 1999. [21] Cliquer. http://users.tkk.fi/ pat/cliquer.html. [22] R. Dick, D. Rhodes, and W. Wolf, “TGFF: Task Graphs for free,” in Proc. Int. Workshop. Hardware/Software Codesign, pp. 97-101, Mar. 1998. [23] P. Pop, P. Eles, T. Pop, and Z. Peng, “An Approach to Incremental Design of Distributed Embedded Systems,” in Proc. ACM/IEEE Design Automation Conf. (DAC) , pp. 450–455, Jun. 2001. [24] Y. Xie and W. Wolf, “Allocation and Scheduling of Conditional Task Graph in hardware/software Co-synthesis,” in Proc. Design, Automation and Test in Europe Conf. (DATE) , pp. 620–625, Mar. 2001. [25] T. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A dynamic voltage scaled microprocessor system,” IEEE Journal of Solid-State Circuits, vol. 35, no.11, pp. 1571-1580, Nov. 2000 [26] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava, “Power Optimization of Variable-Voltage Core-Based Systems,” IEEE Trans. Computer-Aided Design, vol. 18, no.12, pp. 1702-1714, Dec. 1999. [27] Y. Lin, C. Hwang and A. Wu, “Scheduling Techniques for Variable Voltage Lowpower Designs,” ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 2 , pp 81-79, Apr. 1997. [28] R. Mishra, N. Rastogi, D. Zhu, D. Mosse, and R. Melhem, “Energy Aware Scheduling for Distributed Real-time Systems,” International Parallel and Distributed Processing Symposium, pp. 1-9 , Apr. 2003. [29] S. Hua and G. Qu, “Power Minimization Techniques on Distributed Real-Time Systems by Global and Local Slack Management,” IEEE/ACM Asia South Pacific Design Automation Conference, Vol. 2 , pp. 830- 835, Jan. 2005. [30] S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani, 'A Network on Chip Architecture and Design Methodology,' IEEE Computer Society Annual Symposium on VLSI, pp. 117-124, April 2002. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23012 | - |
dc.description.abstract | 本文提出一個新的低耗能排程(energy-aware scheduling)演算法,應用在NoC架構上並使用動態調整電壓來達到省電的效果。在處理器各個核心使用率不高的情況下,透過平行化和動態電壓調整(DVS, dynamic voltage scaling)的技術,以提高各核心使用率來降低功率的消耗。在排程的過程中相較於傳統的方式,我們多考慮了DVS帶來的影響,在減少核心之間的溝通(communication)產生的耗能外也試著去增加執行DVS的機會。在DVS方面把問題轉換成最大點集團(Maximum Weight Clique)問題來解,可以讓DVS的執行更有效率。提出的演算法相較於EAS演算法,可以節省22%的耗能。另外改良過的DVS演算法,相較於PV-DVS演算法,在耗能節省方面有97%的增進。 | zh_TW |
dc.description.abstract | Energy-aware task assignment and scheduling over a many-core network-on-chip (MC-NoC) platform is investigated. For real time applications, time slacks of a preliminary task schedule may be exploited to conserve energy. This can be accomplished by leveraging the dynamic voltage scaling (DVS) technique to slow down clock frequency of certain cores so long as the deadline is met. In this Thesis, the task of fine-tuning an existing task assignment and schedule and using DVS to lower overall energy consumption is formulated as a graph-theoretic maximum weight clique (MWC) problem. An efficient heuristic algorithm is proposed to systematically solve this problem. A unique feature of our approach is concurrently applying DVS to slow down execution of multiple tasks to achieve better energy saving. Extensive simulations are performed to compare this proposed algorithm against leading energy-aware task scheduling algorithm and DVS algorithm. Our algorithm exhibits a 22% more energy saving than the EAS algorithm. As for energy saving in DVS process, our MWC-based method provides a 97% saving improvement over the PV-DVS algorithm. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:37:43Z (GMT). No. of bitstreams: 1 ntu-98-R96943115-1.pdf: 1060309 bytes, checksum: 0ca0b901ea07612b93e42faf535a64d6 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v CHAPTER 1 INTRODUCTION 1 1.1 Scheduling Problem on NoC 1 1.2 Voltage Selection Technique 2 1.3 Contributions on this Thesis 2 1.4 Thesis Organization 3 CHAPTER 2 PRELIMINARIES 5 2.1 Basic Concept of NoC 5 2.2 Previous Work 7 2.2.1 EEGMA 9 2.2.2 CASPER 11 2.2.3 ETAHM 11 2.2.4 The algorithm Zhang et al. proposed 12 2.2.5 The algorithm Varatkar et al. proposed 13 2.2.6 EAS 14 2.3 Problem Description 16 CHAPTER 3 MOTIVATIONAL EXAMPLE 21 CHAPTER 4 PROPOSED ALGORITHMIC SOLUTION 25 4.1 Task Prioritization 26 4.2 Task Assignment 29 4.3 Power Optimization 32 4.4 Re-Scheduling Setup 36 4.5 Repair Process 37 CHAPTER 5 EXPERIMENTAL RESULTS 41 CHAPTER 6 CONCLUSION 47 REFERENCE 49 | |
dc.language.iso | en | |
dc.title | 應用在晶片網路架構上可動態調整電壓的低功率排程 | zh_TW |
dc.title | Energy-Aware Task Scheduling for NoC-based Dynamic Voltage Scalable System | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊佳玲,郭斯彥,熊博安 | |
dc.subject.keyword | 低耗能,任務排程,多核心,動態調整電壓,晶片網路架構, | zh_TW |
dc.subject.keyword | low power,task scheduling,multi-core,DVS,NoC, | en |
dc.relation.page | 51 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-98-1.pdf 目前未授權公開取用 | 1.04 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。