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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Cheng-Hsiao Lin | en |
| dc.contributor.author | 林政校 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:35:20Z | - |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-18 | |
| dc.identifier.citation | [1] Y.-C. Sung, O.-K. Kwon and J.-K. Kim, '10-Bit Source Driver with Resistor-Resistor-String Digital-to-Analog Converter,' SID J. of Society for Information Display, Vol. 14, pp. 371-377, Apr., 2006.
[2] Y.-J. Jeon, H.-M. Lee, S. W. Lee, G. H. Cho, H. R. Kim, Y. K. Choi and M. Lee, 'A Piecewise-Linear 10b DAC Architecture with Drain-Current Modulation for Compact AMLCD Driver ICs,' IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb., 2009, pp. 264-265. [3] C.-W. Lu, 'High-Speed Driving Scheme and Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications,' IEEE J. of Solid-State Circuits, Vol. 39, pp. 1938-1947, Nov., 2004. [4] C.-W. Lu and K.-J. Hsu, 'A High-Speed Low-Power Rail-to-Rail Column Driver for AMLCD Application,' IEEE J. of Solid-State Circuits, Vol. 39, pp. 1313-1320, Aug., 2004. [5] Y.-S. Son, J.-H. Kim, H.-H. Cho, J.-P. Hong, J.-H. Na, D.-S. Kim, D.-K. Han, J.-C. Hong, Y.-J. Jeon, and G.-H. Cho, 'A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs,' IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb., 2007, pp. 142-143. [6] Y.-C. Lai, 'A Comparator-Based Ultra Low-Power Area-Efficient Column Driver Buffer,' in National Taiwan University, Master Thesis,Oct., 2007. [7] D.-K. Yang and S.-T. Wu, Fundamentals of Liquid Crystal Devices. 1st Ed., Wiley & Sons, 2006. [8] Y.-H. Tai, Design and Operation of TFT-LCD Panels. 1st Ed., Wu-Nan Book, 2006. [9] J.-H. Kim, B.-D. Choi, and O.-K. Kwon, '1-Billion-Color TFT-LCD TV with Full HD Format,' IEEE T. Consumer Electronics, Vol. 51, pp. 1042-1050, Nov., 2005. [10] Y. Kudo, A. Akai, T. Furuhashi, T. Matsudo, and Y. Yokota, 'Low-power and High-integration Driver IC for Small-sized TFT-LCDs,' SID Symp. Dig., 2003, pp. 1244-1247. [11] Behzad Razavi, Principles of Data Conversion System Design. 1st Ed., Wiley-Interscience, 1995. [12] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, 'Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies,' IEEE J. of Solid-State Circuits, Vol. 41, pp. 2658-2668, Dec., 2006. [13] T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, 'Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,' IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb., 2006, pp. 220-221. [14] M. J. Bell, 'An LCD Column Driver Using a Switch Capacitor DAC,' IEEE J. of Solid-State Circuits, Vol. 40, pp. 2756-5765, Dec., 2005. [15] Y.-K. Choi, Z.-Y. Wu, K. M. Kim, Y. H. Lee, M. S. Cho, H. S. Kim, D. H. Lee and W.-G. Jung, 'A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICs,' IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb., 2008, pp. 176-177. [16] K. Hashimoto, F. Matsuki, K. Yamashita, K. Sano, W.-C. Lin, J. R. Ayres and M. Edwards, 'A High Resolution LTPS AMLCD with Integrated 8-Bit DAC,' SID Symp. Dig., 2007, pp. 280-283. [17] C.-W. Lu and L.-C. Huang, 'A 10-Bit LCD Column Driver with Piecewise Linear Digital-to-Analog Converter,' IEEE J. of Solid-State Circuits, Vol. 43, pp. 371-378, Feb.,2008. [18] H. Sasaki and T. Taguchi, 'Perceptually Linear Gamma Correction for LCDs,' SID Symp. Dig., 2003, pp.936-939. [19] P.-M. Lee and H.-Y. Chen, 'Adjustable Gamma Correction Circuit for TFT LCD,' ISCAS, pp.780-783, May, 2005. [20] P. Zebedee, M. Brownlow, J. Lock, K. Sano, H. Walton, Y. Kubota, K. Maeda, N. Matsuda and H. Washio, 'A 2.1-in. QCIF+ CG-Silicon LCD with a Low Power Non-Linear DAC,' SID Symp. Dig., 2004, pp. 296-299. [21] K. Bult and G. J. M. Geelen, 'An Inherently Linear and Compact MOST-Only Current Division Technique,' IEEE J. of Solid-State Circuits, Vol. 27, pp. 1730-1735, Dec., 1992. [22] Ken Martin, Digital Integrated Circuit Design. 1st Ed., Oxford University Press, 2000. [23] L. Wang, Y. Fukatsu and K. Watanabe, 'Characterization of Current-Mode CMOS R-2R Ladder Digital-to-Analog Converters,' IEEE Trans. Instr. and Meas., Vol. 50, Dec.,2001,pp. 1781-1786. [24] C. M. Hammerschmied and Q. Huang, 'Design and Implementation of An Untrimmed MOSFET-Only 10-Bit A/D Converter with -79-dB THD,' IEEE J. of Solid-State Circuits, Vol. 33, pp. 1148-1157, Aug., 1998. [25] A. Van den Bosch, M. Steyaert and W. Sansen, “An Accurate Statisical Yield Model Model for CMOS Current-Steering D/A Converters, in Proc. IEEE Int. Symp. Circuits and Systems, 2000, pp. 105-108. [26] M. J. M. Pelgrom, A.C.J. Duinmaijer and A.P. G. Welbers, 'Matching Properties of MOS Transistors,' IEEE J. of Solid-State Circuits, Vol. 24, pp. 1433-1440, Oct., 1989. [27] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC, IEEE J. of Solid-State Circuits, Vol. 33, pp. 1959-1969, Dec., 1998. [28] K. K. Moez, 'Design of a-Si TFT Demultiplexers for Driving Gate Lines in Active Matrix Arrays,' IEEE Trans. Electron Devices, Vol. 52, no. 12, pp. 2806-2809, Dec., 2005. [29] C.-C. Chen, N.-K. Lu, C.-H. Hsu and M.-L. Lee, 'Color-Depth Improvement Using Gamma Voltage Control,' SID Symp. Dig., 2006, pp. 351-354. [30] Y.-S. Son and G.-H. Cho, 'Design Considerations of Channel Buffer Amplifiers for Low-power Area-efficient Column Drivers in Active-Matrix LCDs,' IEEE T. Consumer Electronics, Vol. 54, pp. 648-656, May., 2008. [31] Behzad Razavi, Design of Analog CMOS Integrated Circuits. 1st Ed., McGraw-Hill, 2001. [32] D. A. Johns and K. Martin, Analog Integrated Circuit Design., Wiley & Sons, 1997. [33] T. Itakura, H. Minamizaki, T. Saito, and T. Kuroda, 'A 402-Output TFT-LCD Driver IC With Power Control Based on the Number Colors Selected,' IEEE J. of Solid-State Circuits, Vol. 38, pp. 503-510, Mar., 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22960 | - |
| dc.description.abstract | 隨著行動多媒體裝置的普及，顯示器技術也隨之革命與發展。輕、薄、低功率消耗、低成本等技術都是研究者們所追求的目標。在薄膜電晶體液晶顯示器的驅動系統中，高解析度與低功率消耗的驅動電路是最重要的研究課題。
在液晶顯示器的驅動電路中，行驅動電路消耗最多的功率且決定速度與解析度。許多液晶顯示器的行驅動電路架構被提出。然而在高效能的應用中，為不同顏色的獨立伽瑪校正與更多顯示灰階的設計是必要的。 在這篇論文中，我們提出了一個應用於薄膜電晶體液晶顯示器的行驅動電路，其結合了伽瑪校正的數位類比轉換器與低功率消耗的輸出緩衝器。電路實作上使用標準0.35微米互補金氧半導體製程，其供應電壓為5伏特，此電路的晶片面積為1.32 × 1.48 毫米平方。所設計的行驅動電路在點反轉的操作模式下，能輸出具伽瑪校正的對稱波形，且對輸出通道進行充放電。而伽瑪校正的功能也可根據不同顏色來設計。 | zh_TW |
| dc.description.abstract | For the popularity of mobile multimedia, display techniques also revolute and develop continuously. Light, thin, low power consumption, and cost down are demanded without end for the researchers. The high-resolution and low-power of TFT-LCD drivers are the most important issues in the implementation of display driving system.
Among circuits consisting in the LCD driving system, the column driver consumes the most power and determines the speed and resolution. Several LCD column driver architectures are proposed. However, both independent gamma correction and higher gray-scale capability are necessary in high-performance applications. In this thesis, an integrated gamma-corrected digital-to-analog converter with a low-power buffer for TFT-LCD column drivers is proposed. The whole chip occupies an area of 1.32 × 1.48 mm2 fabricated in TSMC 0.35-µm 5V technology. The column driver can output symmetric gamma-corrected waveforms to charge or discharge channels under the operation of dot inversion, and can be designed for different gamma curve according to individual RGB color. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:35:20Z (GMT). No. of bitstreams: 1 ntu-98-J95921022-1.pdf: 6734087 bytes, checksum: d59fcd3549d2c878ebf230847cb988a6 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Table of Contents
Table of Contents I List of Figures V List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Basic Concepts and System Overview 5 2.1 Basic Concepts 5 2.1.1 Operation Principle of TFT-LCD 5 2.1.2 Addressing of TFT-LCD 7 2.1.3 Pixel Inversion Methods 9 2.1.4 Gamma Correction 13 2.2 System Block Diagram of TFT-LCD Drivers 15 2.2.1 Timing Controller 16 2.2.2 Gate Driver 16 2.2.3 Column Driver 18 2.2.4 Common Reference Voltage Source 20 2.2.5 Voltage Source Regulator 20 2.2.6 Gamma Correction Reference Voltage Source 20 2.3 DAC Architectures 20 2.2.1 Resistor-String DAC 21 2.2.2 Switched-Capacitor DAC 22 2.2.3 Two-Stage Resistor-Capacitor DAC 23 2.2.4 DAC for Gamma Correction 23 Chapter 3 The Design and Analysis of Non-Linear R-2R Transistor-Only Ladder 25 3.1 Introduction 25 3.1.1 The Inherently Linear Transistor-Only Current Division 25 3.1.2 Equivalent Aspect Ratio 27 3.2 Increase Output Current Slope of R-2R Transistors Ladder 29 3.2.1 Increase of the Output Current Slope 30 3.2.2 Decrease of the Output Current Slope 37 3.2.3 Offset the Output Current in R-2R Transistors Ladder 39 3.2.4 Non-Linear R-2R Transistors Ladder 40 3.2.5 Displacement 40 3.2.6 Design Considerations 41 3.2.7 Mismatch 44 3.3 Circuit Implementation in a-Si TFT Process Technology 44 3.3.1 6-bit Linear R-2R TFTs Ladder 45 3.3.2 6-bit Non-Linear R-2R TFTs Ladder 47 3.3.3 Layout Technique and Microphotograph 48 3.3.4 Experimental Results 50 Chapter 4 Circuit Implementation 53 4.1 Proposed System Architecture 53 4.2 Input Registers 54 4.3 Trigger Generator 55 4.4 Output Buffer 56 4.4.1 Comparators 58 4.4.2 Operational Amplifiers 59 4.4.3 Charge Pumps 60 4.4.4 Latch 61 4.5 Proposed 6-bit Gamma-Corrected DAC 62 4.5.1 Linear R-2R PMOS Ladder 63 4.5.2 Decision Logic 64 4.5.3 Control Transistors 65 4.5.4 Current-to-Voltage Converter 66 4.6 Transistor-Level Simulation of Proposed Column Driver 69 4.7 Layout and Performance Summary 73 Chapter 5 Experimental Results of the Proposed Column Driver 75 5.1 Chip Microphotograph 75 5.2 Test Strategy 77 5.2.1 Test Setup 77 5.2.2 Print Circuit Board Design 79 5.3 Experimental Results 79 Chapter 6 Conclusions 83 6.1 Conclusions 83 Bibliography 85 List of Figures Chapter 1 Chapter 2 Fig. 2.1 Liquid crystal and polarizer configurations of 90º TN cell (a) Voltage-off state, (b) Voltage-on state. 6 Fig. 2.2 The active matrix LCD with a TFT as sub-pixel switch. 8 Fig. 2.3 Polarity inversion. 10 Fig. 2.4 The equivalent circuit of liquid crystal and orientation layers. 10 Fig. 2.5 Moving direction of mobile ions. 12 Fig. 2.6 Inversion method (a) Frame inversion, (b) Column inversion, (c) Row inversion, (d) Dot inversion. 13 Fig. 2.7 Gamma curve. 14 Fig. 2.8 The transformation of video data to sensation of human brain. 15 Fig. 2.9 TFT-LCD system structure. 16 Fig. 2.10 System structure of a gate driver. 17 Fig. 2.11 Timing diagram of shift registers. 17 Fig. 2.12 System structure of a source driver. 19 Fig. 2.13 Resistor-string DACs (a) switch type, (b) ROM type. 21 Fig. 2.14 Switched-capacitor DAC. 22 Fig. 2.15 Two-stage resistor-capacitor DAC. 23 Chapter 3 Fig. 3.1 The basic principle of current division. 26 Fig. 3.2 Scaling of the aspect ratio. 27 Fig. 3.3 The equivalent aspect ratio (a) in series, (b) in parallel. 28 Fig. 3.4 A unit cell of the R-2R transistor-only ladder for 1-bit conversion. 29 Fig. 3.5 Linear 6-bit R-2R transistors ladder. 29 Fig. 3.6 Change D2~D6 output current of the 6-bit R-2R transistors ladder. 30 Fig. 3.7 Equivalent circuit of the circuit in Fig. 3.6. 31 Fig. 3.8 Change D3~D6 output current of the 6-bit R-2R transistors ladder. 32 Fig. 3.9 Equivalent circuit of the circuit in Fig. 3.8. 33 Fig. 3.10 Voltages relation between node 3 and node 5. 34 Fig. 3.11 Change D6 output current of the 6-bit R-2R transistors ladder. 35 Fig. 3.12 Equivalent circuit of the circuit in Fig. 3.11. 37 Fig. 3.13 Change D2~D6 output current of the 6-bit R-2R transistors ladder. 37 Fig. 3.14 Equivalent circuit of the circuit in Fig. 3.13. 38 Fig. 3.15 Offset output current in the R-2R transistors ladder. 39 Fig. 3.16 Proposed non-linear R-2R transistors ladder. 40 Fig. 3.17 (a) The design flow graph, (b) The design sequence. 42 Fig. 3.18 Simulation results of settling time for the non-linear R-2R ladder. 43 Fig. 3.19 Channel length variation : -2.5% ~ 2.5%. 44 Fig. 3.20 6-bit linear R-2R TFTs ladder. 46 Fig. 3.21 Simulation current of 6-bit linear R-2R TFTs ladder. 46 Fig. 3.22 Simulation results of 6-bit linear R-2R TFTs ladder (a) INL, (b)DNL. 47 Fig. 3.23 6-bit non-linear R-2R TFTs ladder. 47 Fig. 3.24 Simulation current of 6-bit non-linear R-2R TFTs ladder. 48 Fig. 3.25 Layout of the unit cell in R-2R TFTs ladder. 48 Fig. 3.26 (a) Layout of the 6-bit linear R-2R TFTs ladder, (b) Microphotograph. 49 Fig. 3.27 (a) Layout of the non-linear R-2R TFTs ladder, (b) Microphotograph. 49 Fig. 3.28 Test setup. 50 Fig. 3.29 Measured waveforms (a) Linear, (b) Non-linear. 51 Chapter 4 Fig. 4.1 Architecture of the proposed column driver. 54 Fig. 4.2 (a) The 6-bit input registers, (b) An edge-triggered D-Flip-Flops 55 Fig. 4.3 The trigger generator. 56 Fig. 4.4 Comparator-based column driver buffer. 57 Fig. 4.5 Waveforms of the buffer (a) for the change of the output multiplexer, (b) for the change of input signal. 58 Fig. 4.6 (a) Positive polarity and (b) negative polarity comparators. 59 Fig. 4.7 (a) Positive polarity and (b) negative polarity op amps. 60 Fig. 4.8 (a) Positive polarity and (b) negative polarity charge pumps. 61 Fig. 4.9 The latch. 61 Fig. 4.10 Architecture of the 6-bit gamma-corrected DAC. 62 Fig. 4.11 Simulation of the 6-bit differential PMOS ladder. 64 Fig. 4.12 (a) The decision Logic, (b) n-input NAND gate. 64 Fig. 4.13 The control transistors. 65 Fig. 4.14 The two-stage amplifier (a) N-type input stage, (b) P-type input stage, (c) the bias circuit and start-up circuit, (d) bias circuit. 67 Fig. 4.15 Simulation results of (a) N-type input stage, (b) P-type input stage. 68 Fig. 4.16 System-level of the 6-bit gamma-corrected column driver. 69 Fig. 4.17 Simulation results of the differential R-2R PMOS ladders. 70 Fig. 4.18 Simulation results of the current-to-voltage converters. 71 Fig. 4.19 Simulation results of two neighboring channels under dot inversion. 72 Fig. 4.20 Simulation results of the column driver with 200 pF loading. 72 Fig. 4.21 (a) Layout of the designed column driver, (b) Core of the chip. 73 Chapter 5 Fig. 5.1 The die microphotograph of the designed column driver. 76 Fig. 5.2 Pin configuration. 76 Fig. 5.3 The description of the pin configuration. 77 Fig. 5.4 Test setup. 78 Fig. 5.5 The print circuit board. 79 Fig. 5.6 Measured waveforms of two neighboring channels (a) channel 1, (b) channel 2. 80 Fig. 5.7 Measured waveforms of two neighboring channels under dot inversion. 81 Fig. 5.8 Measured waveforms of two neighboring channels under dot inversion (a) Output loading : 100 pF, (b) Output loading : 200 pF. 82 Chapter 6 List of Tables Chapter 1 Chapter 2 Chapter 3 Table 3.1 The relation between changed slope and the aspect ratio. 39 Table 3.2 The displacement due to changing current slope. 41 Table 3.3 Simulation parameters of settling time. 43 Table 3.4 Design parameters of the linear R-2R TFTs ladder. 46 Chapter 4 Table 4.1 Design parameters of the linear R-2R PMOS ladder. 63 Table 4.2 Design parameters of the control transistors. 65 Table 4.3 Design parameters of the two-stage amplifier. 68 Table 4.4 Simulation Performance Summary. 74 Table 4.5 Performance Comparisons. 74 Chapter 5 Table 5.1 Chip Performance Summary. 82 Chapter 6 | |
| dc.language.iso | en | |
| dc.subject | 點反轉 | zh_TW |
| dc.subject | 薄膜電晶體液晶顯示器 | zh_TW |
| dc.subject | 行驅動器 | zh_TW |
| dc.subject | 伽瑪校正 | zh_TW |
| dc.subject | 數位類比轉換器 | zh_TW |
| dc.subject | gamma correction | en |
| dc.subject | dot inversion | en |
| dc.subject | TFT-LCD | en |
| dc.subject | column driver | en |
| dc.subject | digital-to-analog converter | en |
| dc.title | 具伽瑪校正的六位元數位類比轉換器與低功率緩衝器的行驅動電路 | zh_TW |
| dc.title | A 6-bit Gamma-Corrected DAC with a Low-Power Buffer for Column Drivers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),陳信樹(Hsin-Shu Chen),陳巍仁(Wei-Zen Chen) | |
| dc.subject.keyword | 薄膜電晶體液晶顯示器,行驅動器,伽瑪校正,數位類比轉換器,點反轉, | zh_TW |
| dc.subject.keyword | TFT-LCD,column driver,gamma correction,digital-to-analog converter,dot inversion, | en |
| dc.relation.page | 88 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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