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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂學士 | |
dc.contributor.author | Yong-Chang Chen | en |
dc.contributor.author | 陳永昌 | zh_TW |
dc.date.accessioned | 2021-06-08T04:34:45Z | - |
dc.date.copyright | 2009-08-20 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-19 | |
dc.identifier.citation | [1.1]. United Nations Development Programme (September 2005). Human
Development Report 2005: International Cooperation at a Crossroads-Aid, Trade and Security in an Unequal World. United Nations Development Programme. ISBN 9780195305111 [1.2]. Taiwan Council for Economic Planning and Development website, http://www.cepd.gov.tw/ [1.3]. http://robotics.eecs.berkeley.edu/~pister/SmartDust [2.1]. L. Wang, Y. Fukatsu, and K. Watnabe, “Characterization of current-mode CMOS R-2R ladder digital-to-analog converters,” IEEE Trans. Instrum. Meas., vol. 50, no.6, pp. 1781-1786, Dec. 2001 [2.2]. Shao-Yi Chien, “Computer-aided VLSI System Design Cell-Based Design Flow and Tools” handout pp.8, Graduate Institute of Electronics Engineering, National Taiwan University.2008 [2.3]. Sachin Sapatnekar, “Efficient Retiming of Large Circuits”, IEEE Transactions on very large scale integration (VLSI) System [2.4]. Frank Emnett and Mark Biegel, “Power Reduction Through RTL Clock Gating” SNUG San Jose 2000 [3.1]. Yi-Ming Chang, “An Efficient Data Search and Replication Strategy in Wireless Sensor Networks”, National Dong-Hwa University MS. Thesis, July 2006 [3.2]. Chang-Jiu Chen, Wei-Min Cheng, Ruei-Fu Tsai, Hung-Yue Tsai, and Tuan-Chieh Wang, “A Pipelined Asynchronous 8051 Soft-core Implemented with Balsa', National Chiao-Tung University [3.3]. Chammika Mannakkara, Tomohiro Yoneda, “Pipeline Controller Based on Acknowledgement Protocol” National Institute of Informatics Graduate University for Advanced Studies Tokyo, Japan [3.4]. http://www.cs.iastate.edu/~prabhu/Tutorial [3.5]. Kai-Wen Yeh, “Microcontroller Design for Wireless Sensor Network”, National Taiwan University MS. Thesis. July 2008 [3.6]. http://www.mikroe.com/ [3.7]. EPCglobal Inc.,EPCTM “ Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz - 960 MHz Version 1.0.9”. 2004 [3.8]. Rafey Mahmud, “Techniques to make clock switching glitch free”, EETimes, http://www.eetimes.com/story/OEG20030626S0035 [4.1]. Zhi-Cheng Chuang, “Microcontroller Design and Application for Wireless Bio-Sensor Network”, NTU MS. Thesis, 2007 [4.2]. Kai-Wen Yeh, “Microcontroller Design for Wireless Sensor Network”, NTU MS. Thesis, 2008 [4.3]. http://en.wikipedia.org/wiki/Fault_coverage [4.4]. GlobalCAD, Inc., http://www.gcadinc.com/index.html | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22947 | - |
dc.description.abstract | 全球人口正在快速的老化,許多國家包括台灣皆已邁入聯合國定義之高齡社會,因此如何有效輔助老人生活將會是未來的重要議題。因為半導體製程技術的進步,使得低成本,體積小,耗電量低的系統單晶片已經成為一個主要的趨勢。本論文實現一應用於生醫上無線感測網路的感測節點,將可以適用於遠端照護的需求。
本論文使用台積電0.35um 2P4M CMOS製程實現一無線生醫感測節點之系統單晶片,其內部電路包含微控制器、OOK接收器、ASK傳送器、儀器放大器、類比數位轉換器、轉阻放大器、類比多工器及電壓調節器。微控制器為一可程式化並相容於標準8051指令集的微控制器,核心部份採用別於以往的真實五級管線化架構來提升整體的效能。 可程式化微控制器資料匯流排為8 bits,位址匯流排12 bits,共可執行111個指令,具備256位元組的資料記憶體與4096位元祖的程式記憶體,兩組計數器,除頻器,兩組具備循環冗餘檢查的通用非同步收發模組,8種中斷源。最高時脈可達40MHz,功率消耗為1.135mA當一般應用於4MHz。晶片面積大小為3167um*3396um。 | zh_TW |
dc.description.abstract | Owing to the Population ageing in the world, many countries include Taiwan have become an aged society which is defined by United Nations. How to assist senior citizens’ life will become an important topic in the future. Depending on the advancement of semiconductor manufacturing technology, it has become a major trend presently to implement a small, low-cost and lower-power system-on-a-chip. This thesis achieved a kind of sensor applied to biomedicine in Wireless Sensor Network, which could be supplied the demand for distance medical treatment.
We used TSMC 0.35 μm 2P4M CMOS process to achieve a system-on-a-chip used as a sensor node in Wireless Bio-Sensor Network. The chip includes Microcontroller, On/Off Keying receiver, Amplitude-Shift Keying transmitter, Instrument Amplifier, Analog-to-Digital Convertor, Trans-Impedance Amplifier, Analog Multiplexer and Voltage Regulators. The Microcontroller is programmable and compatible with standard 8051 Instruction Set. We use a new and real five-stage pipeline architecture to improve overall system performance. The programmable Microcontroller contains 8-bits data bus and 12 bits address bus, it can execute 111 instructions. It also equips 256 bytes data memory and 4096 bytes program memory, two timers, clock-divider, two Universal Asynchronous Receiver/Transmitter with Cyclic Redundancy Checks, 8 types of interrupt. Maximum clock rate of the microcontroller can achieve 40MHz. Power consumption is 1.135mA when the applied rate is 4MHz in general. Total chip area of the SOC is 3167μm*3396μm. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:34:45Z (GMT). No. of bitstreams: 1 ntu-98-J96921038-1.pdf: 2205822 bytes, checksum: a5612ab4d812ea996bc3307252012d53 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Chinese Abstract I
English Abstract III List of Contents V Index of Figures VII Index of Tables XI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 1.3 References 5 Chapter 2 Cell-Based IC Design 7 2.1 IC Design Flow 7 2.1.1 Cell-Based IC Design 7 2.2 Low-Power Design Methods 10 2.2.1 Retiming 10 2.2.2 Clock-Gating 11 2.3 References 13 Chapter 3 A Programmable MCU for Wireless Sensor Node SOC 15 3.1 Wireless Sensor Network With MCU 15 3.1.1 Wireless Sensor Network 15 3.1.2 MCU 17 3.2 Programmable Microcontroller Architecture and Feature 18 3.2.1 Pipeline Processor 20 3.2.2 Instruction Fetch 21 3.2.3 Instruction Decode and Register File Read 24 3.2.4 Execution or Address Calculation 25 3.2.5 Data Memory Access 27 3.2.6 Write Back to Register File 31 3.2.7 Pipeline Controller 32 3.2.8 Branch Predictor 37 3.2.9 Interrupt 41 3.3 Timer and Clock Source 43 3.3.1 Timer / Counter Mode 43 3.3.2 Clock-Divider 45 3.4 Peripherals 46 3.4.1 EEPROM and Rom Loader 46 3.4.2 UART 47 3.4.3 SPI 49 3.4.4 Power Management 49 3.5 References 53 Chapter 4 System-On-A-Chip for Wireless Sensor Node 55 4.1 System-On-a-Chip Overview 55 4.2 RF and Analog Circuits 58 4.2.1 OOK Receiver 58 4.2.2 Instrument Amplifier 60 4.2.3 Trans-Impedance Amplifier 61 4.2.4 Analog Multiplexer 62 4.2.5 Successive Approximation ADC 63 4.2.6 ASK transmitter 65 4.2.7 Voltage Regulator 66 4.2.8 Crystal Oscillator 68 4.2.9 Power-On-Reset Circuit 69 4.3 Measurement for Microcontroller 70 4.3.1 Verification of Microcontroller 70 4.3.2 PCB Design 73 4.3.3 Testing Setup and The Result 76 4.3.4 Specification Summary 81 4.4 References 83 Chapter 5 Conclusion 85 Appendix A Related Patents Search and Analysis 87 | |
dc.language.iso | en | |
dc.title | 應用於無線生醫感測網路之微控制器設計 | zh_TW |
dc.title | Microcontroller Design for Wireless Bio-Sensor Network | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 孟慶宗,張培仁,邱弘緯,陳筱青 | |
dc.subject.keyword | 無線感測網路,系統單晶片,微控制器,8051,管線結構, | zh_TW |
dc.subject.keyword | Wireless sensor network,SOC(System-on-a-Chip),Microcontroller,8051,Pipeline Architecture, | en |
dc.relation.page | 91 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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