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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22911
標題: | 雙向晶片網路架構之效能感知程序映射 Performance-aware Task Mapping for Bi-directional NoC Architecture |
作者: | Yueh-Chi Lin 林玥其 |
指導教授: | 陳少傑(Sao-Jie Chen) |
關鍵字: | 雙向晶片網路架構,晶片網路架構,映射, bi-directional NoC,BiNoC,NoC,mapping, |
出版年 : | 2009 |
學位: | 碩士 |
摘要: | 本文針對雙向晶片網路架構(bi-dirctional NoC)提出一個效能感知程序映射演算架構,包含程序叢集(task clustering)及程序映射(task mapping)兩個演算法。利用雙向晶片網路架構的資料傳送通道可被調控之特性,在各個時間點分配通道給需要的資料流,以達到提升系統效能之效果。實驗結果顯示本文所提出之效能感知程序映射演算架構可有效降低系統之執行時間,提升系統在雙向晶片網路架構上之效能。 In this Thesis, we propose a performance-aware task mapping algorithm for BiNoC (bi-directional network-on-chip) architecture. The whole framework contains two phases: task clustering and task mapping. For a given task graph and a BiNoC topology, the task clustering phase partitions a task graph into appropriate clusters to minimize the system parallelization time. The task mapping phase employs an SA-based (simulated annealing-based) algorithm which maps clusters of TCG (task communication graph) to PEs (processing elements) injectively. The SA-based algorithm uses real execution time as the cost function and considers the negative effect caused by contentions. Since the channel direction is configurable in a BiNoC, our approach makes use of this characteristic to allocate channel admission to the communication demands and lead to a low system execution time. Experimental results show that, compared to other existing mapping approaches for performance-aware purpose, our approach achieves a significant decrease in packet latency. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22911 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-98-1.pdf 目前未授權公開取用 | 1.18 MB | Adobe PDF |
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