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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Hui-Hsien Liu | en |
dc.contributor.author | 劉慧賢 | zh_TW |
dc.date.accessioned | 2021-06-08T04:31:55Z | - |
dc.date.copyright | 2009-10-05 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-09-24 | |
dc.identifier.citation | [1] Federal Communications Commission, “Notice of Proposed Rulemaking,” March, 2009
[2] Pui-in Mak, Seng-Pan U and Rui P.Martins, “Transceiver Architecture Selection: Review, State-of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, 2007. [3] M. Sharifkhani, M. Sachdev, “A Phase-Domain Continuous-Time 2nd-Order Delta-Sigma Frequency Digitizer,” IEEE Custom Integrated Circuit Conf., 2006 [4] Hans Gustat and Frank Herzel, “Integrated FSK Demodulator With Very High Sensitivity,” IEEE J. Solid-State Circuits, vol. 38, pp. 357-360, Feb. 2003 [5] Y.-H. Liu and T.-H. Lin, “A Wideband PLL-based G/FSK Transmitter in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, Sep.,2009 [6] Behzad Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall PTR, 1998. [7] C. J. Tung, Y. H. Liu, H. H. Liu, T. H. Lin, “A 400-MHz Super-regenerative Receiver with Digital Calibration for Capsule Endoscope Systems in 0.18-μm CMOS,” IEEE VLSI-DAT, 2008. [8] J. Y. Chen, M. P. Flynn, and J. P. Hayes, “A Fully Integrated Auto-calibrated Super-regenerative Receiver in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, pp. 1976-1985, Sept. 2007. [9] P. Favre, N. Joehl, A. Vouilloz, P. Deval , C. Dehollain, and M. Declercq, “A 2-V 600-μA 1-GHz BiCMOS Super-regenerative Receiver for ISM Applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2186-2196, June 1998. [10] J. R. Whitehead, Super-Regenerative Receivers. Cambridge, U.K.: Cambridge Univ. Press, 1950 [11] C. F. Liang, H. L. Chu, S. I. Liu, “10-Gb/s Inductorless CDRs with Digital Frequency Calibration,” IEEE Trans. On Circuits and Systems, Oct. 2008, pp. 2514-2524. [12] Napong Panitantum, Kartikeya Mayaram, and Terri S. Fiez, “A 900-MHz Low-power Transmitter with Fast Frequency Calibration for Wireless Sensor Networks,” IEEE Custom Integrated Circuits Conf., Sept. 2008, pp. 595-598. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22881 | - |
dc.description.abstract | 本論文中將提出兩個操作400 MHz頻段之用於植入式醫療通訊系統的接收器設計。在第二章及第三章將討論所提出的用作解調GFSK調變訊號之接收器,在第四章及第五章將討論另一個提出的用作解調OOK調變訊號之接收器。
本論文所提出之GFSK 接收器採用連續時間三角積分鎖相迴路的架構。GFSK 訊號的資訊是儲存在它的頻率中,因此比採用其他調變方式的訊號更能抵抗頻帶中的雜訊。本接收器結合了GFSK訊號的解調及數位化,且直接操作在400 MHz 的頻率。本接收器是用點一八微米金氧半製程來實現,消耗電流為16.45毫瓦特,最大資料接收率為2 Mbps。 本論文所提出之OOK 接收器採用超再生架構,其架構較為簡單且消耗功率較低。在本接收器中,額外加上頻率校正電路去調整振盪器之中心頻率來抵抗製程偏異之影響,雖然鎖相迴路也能校正振盪器頻率,但是其鎖定時間較長,耗電較多。我們提出的頻率校正迴路能夠於2.7 μs內校正振盪器頻率至所需頻段。本接收器最大資料接收率之為1 Mbps。本超再生式接收器是使用點一八微米金氧半製程來實現,量測結果顯示消耗功率為2.2毫瓦特。 | zh_TW |
dc.description.abstract | In this work, two low-power receivers operating in the 400 MHz frequency band are designed for bio-medical implantable applications. One of the receivers is for Gaussian Frequency Shift Keying (GFSK) demodulation and will be discussed in chapter 2 and chapter 3. The other one is for On-Off Keying (OOK) demodulation and will be discussed in chapter 4 and chapter 5.
The proposed GFSK receiver is a frequency digitizer adopting the structure of a continuous time delta-sigma PLL. The information of a GFSK signal is stored in its frequency; therefore, it is much more robust against channel noise than signals using other modulation methods. The proposed receiver architecture combines the demodulation and digitization process of GFSK modulated signals. The operation is done directly at a high carrier frequency of 400 MHz. The proposed design is fabricated in a 0.18-μm CMOS technology. It consumes 15.45 mW and achieves a data rate of 2 Mbps. The proposed OOK receiver adopts the architecture of a super-regenerative receiver. This architecture is simple and consumes low power. Because of PVT variations, a frequency calibration circuit is needed to adjust the oscillator center frequency to the designed band. Although this can be done by a phase-locked loop, its locking time is too long and consumes much power. In this work, a fast digital frequency calibration circuit is proposed and the maximum tuning time is just 2.7 μs. The receiver is capable of achieving a maximum data rate of 1 Mbps. The proposed super-regenerative receiver, fabricated in TSMC 0.18-μm CMOS process, consumes only 2.2 mW. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:31:55Z (GMT). No. of bitstreams: 1 ntu-98-R96943041-1.pdf: 1297325 bytes, checksum: 87814cecd6dfd93df3e77f006a44fab5 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of GFSK Receiver 3 2.1 Modulation Schemes 3 2.1.1 Frequency Modulation 3 2.1.2 Frequency Shift Keying Modulation 3 2.1.3 Gaussian Frequency Shift Keying Modulation 4 2.2 GFSK Receiver Architecture 4 2.2.1 Hartley and Weaver Receiver 5 2.2.2 PLL-based Receiver 6 Chapter 3 A Continuous-time 2nd-Order delta-sigma Frequency Digitizer 9 3.1 Introduction 9 3.2 Proposed Receiver Architecture 9 3.3 Design Flow of the Proposed Receiver Architecture 13 3.4 Proposed Delta-sigma modulated Phase Rotator (delta-sigma-PR) 15 3.4.1 Operation Principle of the proposed delta-sigma-PR 15 3.4.2 Noise Analysis of the proposed delta-sigma-PR 19 3.5 Noise Analysis of the Proposed Receiver 21 3.6 Circuit Implementations 22 3.6.1 LNA 22 3.6.2 Mixer 24 3.6.3 Loop Filter 29 3.6.4 Quantizer 31 3.6.5 Current-steering DAC 33 3.6.6 Sigma-delta-PR 34 3.7 Overall System Simulation Results 36 3.8 Conclusions 40 Chapter 4 Introduction of Super-Regenerative Receiver 41 4.1 Introduction 41 4.2 Theory of Super-regeneration 42 4.2.1 Quench Signal Waveform and Selectivity of a Super-regenerative Receiver 45 Chapter 5 Proposed Super-regenerative Receiver with Fast Digital Calibration 47 5.1 Introduction 47 5.2 Proposed Super-Regenerative Architecture 47 5.3 Circuit Implementations 49 5.4 Frequency Calibration 52 5.4.1 Operation Principle 52 5.4.2 Comparison with Other Calibration Methods 56 5.5 Q-enhancement and Pulse-width Adjustment 57 5.6 Measurement Results 58 5.6.1 Performance Summary 60 5.7 Conclusions 62 Chapter 6 Conclusions and Future Work 63 6.1 Conclusions 63 6.2 Future work 63 References 65 | |
dc.language.iso | en | |
dc.title | 用於植入式生醫用途之400 MHz 射頻接收器設計 | zh_TW |
dc.title | Design of 400 MHz RF Receivers for Bio-medical Implantable Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳信樹(Hsin-Shu Chen),魏駿愷(Derrick Wei) | |
dc.subject.keyword | 生醫,射頻,接收器, | zh_TW |
dc.subject.keyword | bio-medical,RF,receivers, | en |
dc.relation.page | 66 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-09-24 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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