具疊接式除頻器之低功耗互補式金氧半導體射頻鎖相迴路之設計研究

Abstract

高頻以及高速鎖相迴路在現代有線或是無線通訊系統中扮演了一個重要的角色，然而高頻的鎖相迴路在實現上有相當的難度，故成為在各大國際期刊與會議的熱門題材。在本論文中主要介紹了使用CMOS製程所實現的各種用途之射頻鎖相迴路應用，而驗證鎖相迴路中的高頻壓控振盪器與除頻鍊為此論文首要驗證之電路，待電路驗證無誤後進行第二階段的設計，也就是實現整體鎖相迴路。以TSMC CMOS 0.18um，先後實現出24-GHz 鎖相迴路之前端電路設計、應用於汽車防撞雷達系統之24-GHz低功耗鎖相迴路。在這些電路中我們廣泛的使用了變壓器型態之壓控振盪器，來達到較低之功耗、較好之相位雜訊以及更大的輸出功率。並使用了疊接除法器的方式來達到電流再利用以減低功耗。 第一章大致的描述了鎖相迴路所需要之基本元件特性以及設計要點。接著在第二章提出一個24-GHz變壓器形態之壓控振盪器與除頻鍊揭開了製作24-GHz鎖相迴路之序幕，整體功耗為45mW而其相位雜訊為-93dBc/Hz@1-MHz。前端除頻鏈在鎖相迴路中乃相當重要之部分，高頻部分的精準度能夠掌握後，實現一個鎖相迴路指日可待。爾後，將集聚先前經驗，將驗證過的24-GHz 鎖相迴路前端，加以改版在第三章設計成應用於汽車防撞雷達系統之超低功耗24-GHz鎖相迴路，達到超低功耗29.8mW,低相位雜訊:-122dBc/Hz@10-MHz以及20.8-GHz to 23.37-GHz 之寬操作範圍。

In present generation, high-frequency and high-speed phase-lock-loop plays an important role in wireline or wireless communication systems. However, high frequency PLL has considerable difficulty in realization. Thus, it has become a popular topic in the IEEE journals and conferences. In this thesis, a variety of PLLs has been proposed and fabricated in CMOS technology. The first step of implementation of the PLL is to accomplish a VCO and high-frequency divider chain, which is the most difficult part of high speed PLL. Once the VCO and high-frequency divider chain has been proven and measured correctly, the rest parts of the PLL such as PFD, CP, loop-filter, and static dividers will be fulfilled in my next work in chapter 3, and then the phase-lock-loop is complete. By using TSMC CMOS 0.18μm process, this thesis has proposed a 24-GHz PLL front-end circuit design, and an ultra low-power 24-GHz Phase-Lock-Loop for collision avoidance radar system. In those works, we widely use a wide range of transformer feedback voltage control oscillator, achieving lower power consumption issue and better phase noise and higher output power. And using the cascade divider to achieve the current re-use to minimize the power consumption. The first chapter describes the general use of the basic phase-lock-loop device characteristics and design features. In chapter 2, a 24-GHz transformer feedback VCO and divider chain opened a prelude to making 24-GHz PLL, consuming DC power of 45mW and the measured phase noise is -93dBc/Hz @ 1-MHz. Later on, gathering previous experience of circuits implementation, the 24-GHz PLL front-end has been modified and accomplish into an ultra low-power PLL in chapter 3, consuming DC power of 29.8mW, ultra low phase noise: -122dBc/Hz @ 10-MHz and wide tuning range of 20.8-23.37-GHz.